Hi, I have a custom board based on the P1010RDB-PA using Micron NAND MT29F8G08ABABA. Currenlty we have ported over to SDKv1.7, however these same issues occur with SDKv1.5 as well. With SDKv1.5 I had patched U-Boot to add our chip however adding these changes to SDKv1.7 was not needed for the chip to operate. It appears this issue only occurs with some of the MT29F8G08ABABA NAND chips (we have multiple boards) causing me to belive something is on the edge of working.
The nand chip is programmed by the U-Boot boot loader with a ~30MB file to a 40MB nand partition starting at offset 0x0D600000 . The process of writing to the chip proceeds until the verify portion. Upon verification of the chip the read of a block will fail. Manually attempting to read that block resulted in an error (-74) so I cannot be sure if the block was ever programmed or not.
Thanks for any input you may have,
Matt
Example of Failure:
NAND boot...
Second program loader running in sram...
Tertiary program loader running in sram...
U-Boot 2014.07QorIQ-SDK-V1.7+g659b6a2 (Feb 20 2015 - 11:04:31)
CPU: P1010E, Version: 2.0, (0x80f90020)
Core: e500, Version: 5.2, (0x80212152)
Clock Configuration:
CPU0:800 MHz,
CCB:400 MHz,
DDR:333.333 MHz (666.667 MT/s data rate) (Asynchronous), IFC:100 MHz
L1: D-cache 32 KiB enabled
I-cache 32 KiB enabled
Board: DAXUS 42657-xxx, Boot from NAND
I2C: ready
SPI: ready
DRAM: Detected UDIMM
1 GiB (DDR3, 32-bit, CL=5, ECC off)
Now running in RAM - U-Boot at: 3fef0000
L2: 256 KiB already enabled
NAND: 1024 MiB
MMC: FSL_SDHC: 0
EEPROM: No MAC Address Found
PCIe1: Root Complex of mini PCIe Slot, no link, regs @ 0xffe0a000
PCIe1: Bus 00 - 00
PCIe2: Root Complex of PCIe Slot, x1 gen1, regs @ 0xffe09000
02:00.0 - 10ee:0007 - Memory controller
PCIe2: Bus 01 - 02
In: serial
Out: serial
Err: serial
Net: eTSEC1 [PRIME]
Hit any key to stop autoboot: 0
=>
=> run update_system_usb
(Re)start USB...
USB0: USB EHCI 1.00
scanning bus 0 for devices... 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
reading /amadx/uImage.dtb
23395 bytes read in 35 ms (652.3 KiB/s)
NAND erase: device 0 offset 0xca00000, size 0x200000
Erasing at 0xcb80000 -- 100% complete.
OK
NAND write: device 0 offset 0xca00000, size 0x5b63
23395 bytes written: OK
reading /amadx/rootfs.ext2.gz.u-boot
23403522 bytes read in 1050 ms (21.3 MiB/s)
NAND erase: device 0 offset 0xd600000, size 0x2800000
Erasing at 0xfd80000 -- 100% complete.
OK
NAND write: device 0 offset 0xd600000, size 0x1651c02
NAND write to offset d600000 failed -5
0 bytes written: ERROR
=>
Current NAND Settings used (taken from P1010RDB.h I can provide the whole file if needed)
....
/* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3 0x0
....
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
| CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
