P1010 L1 CACHE

[tsybezoff]

Please, i need help!

I wanna to use L1 cache with L2 cache in my project at p1010. I set up L2, but have a some questions about L1.
1. Can i use L1 Cache in RAM, or only in ROM
2. How to setup L1 Cache??? anybody have an example????
Example in P1010RDB_init.c doesn't work in my project((((

[alexander_yakov]

1. Yes you can use L1 cache for both ROM and RAM

2. L1 cache initialization is quite simple - you need only to enable and invalidate. Below is a part of L1 cache initialization from cache.c file distributed with our CodeWarrior

void l1_cache_init()

{

// Enable and Invalidate L1 DataCache

  asm("mfspr r5,1010");  /* Read in L1CSR0 spr contents  */

  asm("ori  r5,r5,0x0003");  /* Set CE and CFI bit */

  asm("andi. r6,r5,0xFFFD");  /* Clear the CFI bit for the final store */

  asm("mtspr 1010,r5");

  asm("isync");

  asm("isync");

  asm("mtspr 1010,r6");        /* Store the final value */

  asm("isync");

  asm("isync");

//Enable and Invalidate Inst Cache

  asm("mfspr r5,1011");  /* Read in L1CSR1 spr contents  */

  asm("ori  r5,r5,0x0003");  /* Set ICE and ICFI bit */

  asm("andi. r6,r5,0xFFFD");  /* Clear the CFI bit for the final store */

  asm("mtspr 1011,r5");

  asm("isync");

  asm("isync");

  asm("mtspr 1011,r6");        /* Store the final value */

  asm("isync");

  asm("isync");

}

Have a great day,
Alexander

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[tsybezoff]

Спасибо, Александр)
твой код работает у меня в RAM,но не работает в ROM. Я так понимаю, это из-за неправильной моей настройки TLB, MMU и тд. Можешь прикрепить твой файл с настройками под ROM, где есть функция usr_init, по-моему. Там как раз идет описание MMU, TLB, CCRSBAR, DDR.