Memory Mapping in P1015

[pavankumarg]

Hi,

I am currently using a P1015 based custom board which is to be booted using U-boot. I am currently planning to have a custom memory mapping for the board.

The memory mapping of the custom board is as follows:

0x0000_0000 - 0x0FFF_FFFF    DDR3 (Size - 256M)

0x1010_0000 - 0x101F_FFFF    NVRAM (Size - 1M)

0x1030_0000 - 0x122F_FFFF    FPGA  (Size - 32M)

0xF7F0_0000 - 0xF7FF_FFFF   CCSR (Size - 1M)

0xF800_0000 - 0xF8FF_FFFF    Boot Flash (Size - 16M)

Am I correct in assuming that the memory mapping can be changed to suit our requirements. Or are there any constraints to be followed in the memory mapping. Please advice.

[r8070z · Accepted solution]

Have a great day,

Yes the memory mapping can be changed. Notice in the memory controller you should set base address aligned to the bank size. I.e. for 32 M you cannot set 0x1030_0000 as base address. Set for example 0x1200_0000.

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[pavankumarg]

Should the constraint of setting the base address aligned to bank size be followed for FPGA strictly, because the FPGA's internal memory mapping has been done using 0x1030_0000 as the base address. Also should this alignment of base address mentioned by you be followed for other devices too (like the NVRAM or CCSR) ?

[r8070z]

Have a great day,

Actually external device memory map and memory controller (eLBC) bank sizes can be different. The memory controller bank size is set in the bank option register as bit mask for address. Due to that continuous memory block will be aligned on its size boundary. You can set bank memory size greater than the FPGA requires and use only unaligned part of it.

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