Memory Access of secondary core in U-Boot

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Memory Access of secondary core in U-Boot

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mirkoliebender
Contributor II

Hello,

I'm using a P4080 Rev 2.0 and I'm trying to get the secondary core to run some standalone code. 

The code is rather simple, accesses a memory location and writes some data.

e.g.:

unsigned long volatile * const data_addr = (unsigned long*) 0x0;
*data_addr = 0xffffffff;

This would write 0xffffffff to memory location 0x0.

I'm using the U-Boot command "cpu 1 release ADDR - - -" to get the core out of spin to start the program. ADDR is the memory location of the standalone application. Until this point everything works. The code even executes (BDI3000 tells me, that the pc is set correctly and running...I even confirmed that by changing some registers and reading them via debugger).

My problem is the memory access. I'm not very familiar with the memory subsystem of the P4080 and I guess there are some more steps necessary to be able to access memory, but maybe you could point me in the right direction.

Thanks in advance.

Regards, Mirko

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alexander_yakov
NXP TechSupport
NXP TechSupport

Starting from e500 core, the core can not access physical memory without prior configuration of MMU. For boot address the core has one MMU page pre-defined after reset, but all other MMU configurations must be done explicitly before memory access.


Have a great day,
Alexander

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alexander_yakov
NXP TechSupport
NXP TechSupport

Starting from e500 core, the core can not access physical memory without prior configuration of MMU. For boot address the core has one MMU page pre-defined after reset, but all other MMU configurations must be done explicitly before memory access.


Have a great day,
Alexander

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mirkoliebender
Contributor II

Hello alexander,

thank you  for your answer. 

I took your advice and I'm now trying to fully understand the MMU configuration.

I believe to successfully access memory from core1 I need to add the correct TLB entry.

Lets assume I want to access the first 1GiB of memory from core1. Since the TLB entry for that memory region in core0 doesn't feature memory coherency be default, I took the liberty and set MAS2_M while TLB configuration of U-Boot.

For core1 I figured I had to put the same entry into the TLB, so I basically copied the TLB configuration of that entry (just changed the access codes). I'm basically using the following code to set it:

int main()
{
    write_tlb_entry(0x10070000, 0xc0000a00, 0x4, 0x3f, 0);
    /* tlb: 0x1,
       epn: 0x0,
       rpn: 0x2c,
       perms: 0x3f,
       wimge: 0x4,
       ts: 0x0,
       esel: 0x7,
       tsize: 0xa,
       iprot: 0x1
     */
}


void write_tlb_entry(int mas0, int mas1, int mas2, int mas3, int mas7)
{
    asm volatile(
     "mtspr     %0,%6;" /* Write MAS0 */
     "mtspr     %1,%7;" /* Write MAS1 */
     "mtspr     %2,%8;" /* Write MAS2 */
     "mtspr     %3,%9;" /* Write MAS3 */
     "mtspr     %4,%10;" /* Write MAS7 */
     "li     3,0;"
     "mtspr     %5,3;"   /* Write Mas8 */
     "isync;"
     "tlbwe;"            /* TLB Write Entry */
     "msync;"
     "isync" : : "i"(MAS0), "i"(MAS1), "i"(MAS2), "i"(MAS3), "i"(MAS7), "i"(MAS8),
        "r"(mas0), "r"(mas1), "r"(mas2), "r"(mas3), "r"(mas7));
}
‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

Unfortunately I'm stuck with a TLB Error Interrupt every time I try to set the entry. 

Maybe you can help me to figure out what I'm missing.

Best regards,

Mirko

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sinanakman
Senior Contributor III

Hi Mirko

Since you mentioned you are using a BDI3000 I wonder if you could just put a break point

in your code before it accesses memory and use BDI's WTLB commands to create entries

to TLBs (there are some examples in BDI's User Manual). You could then also use TLB0

and TLB1 commands to display the TLB entries. You can test if accessing the memory

works via BDI by first selecting MEMACC CORE and then issuing an MD commands to display

memory. Once this works you could test your code for accessing the memory and bring the

TLB settings into your code.

Hope this helps

Regards

Sinan Akman

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mirkoliebender
Contributor II

Nice trick. Thanks.

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sinanakman
Senior Contributor III

Hi Mirko, did this finally help to solve your problem ?

Hope you were able to resolve this.

Regards

Sinan Akman

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mirkoliebender
Contributor II

Well in the end I discovered that there is already a TLB configuration for a small memory region on envery core that turned out to be enough for me. So basically for my application I stick to this region and everything is fine. In case one needs more than this (I think it was just a few MB) the TLB needs to be configured correctly.
Thank you all for your help.

Best Regards, 

Mirko

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