Machine check error with LD with LDG set

[richardvandebun]

On a p2041 a machine check exception is raised with LD and LDG bits sets. From the datasheet the errors could be cache parity errors, which to me are CPU silicon faults, or L2MMU multi-way hit or CoreNet Bad Data. 

I want to know what can cause the latter two errors. Can someone please explain the two errors?

[ufedor]

For the "L2MMU multi-way hit" description please refer to the e500mc Core Reference Manual, Table 4-5. Machine Check Exception Sources.

The "CoreNet Bad Data" condition is described after the Table 4-6. Error Report Definitions of the e500mc Core Reference Manual.