Is it possible to enable or disable DDR also using SRAM (CPC) in p4080?

cancel
Showing results for 
Search instead for 
Did you mean: 

Is it possible to enable or disable DDR also using SRAM (CPC) in p4080?

Jump to solution
597 Views
hymalaibello
Contributor III

Hello!

I want to know if  it  is possible to enable or disable DDRs also using SRAM (CPC) in p4080? I would like to use CPC in SRAM mode with the DDRs enabled, get the data  then ,send the data by serial port and do the same but with the DDRs  disabled.

Thanks!

Regards,

Hymalai Bello

Labels (1)
1 Solution
167 Views
yipingwang
NXP TechSupport
NXP TechSupport

Hello Hymalai,


I received your initialization file.


1. For DDR controllers without interleaving.

a. define separate LAWs(done)

b. DDR controller registers configuration

CS0_BNDS

Differnet bank for both controllers, for example MC1:CS0_BNDS 0x0000001F MC2:CS0_BNDS 0x0060007F

DDRx_CSn_CONFIG[INTLV_EN] diabled(done)

DDRx_DDR_SDRAM_CFG[BA_INTLV_CTL] disabled(done)



2. As your description previously, you said you wanted to use CPC as SRAM and DDR together, but I didn't find you allocate LAW for SRAM in the initialization file.

In the initialization file, if the SRAM is not needed, please don't allocate TLB entries for it (TLB14 and TLB15).

If you want to use SRAM, please make sure the address allocation is not overlapped with DDR.


You didn't mentioned what problem you encountered, please feel free to let me know if the problem remains.


Have a great day,
Yiping

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

View solution in original post

7 Replies
167 Views
yipingwang
NXP TechSupport
NXP TechSupport

Hello Hymalai,


As we discussed previously, you could set DDR_SDRAM_CFG[MEM_HALT] bit to stop DDR controller, and disable memory controller via DDR_SDRAM_CFG[MEM_EN]=0. In your program, please prevent any access to DDR controller before disable DDR controller.

How do you configure CPCx_CPCSRCR0, do you enable interleaving in your program?

The attached is CodeWarrior initialization file used for CPC as SRAM, please refer to CPC section.


Have a great day,
Yiping

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 Kudos
167 Views
hymalaibello
Contributor III

Hi!

I need to disable only one of the DDR controller, but the program stops.  In the configuration of the CPC as SRAM  Interleaving is disabled. But in the Init_core file, the LAW configuration of DDR 0x8140001E so, that mean that  the interleaving mode in DDR is enabled, but when I try to disable it says Error Writing memory in the debug.

Thanks!

Regards!

Hymalai Bello

0 Kudos
167 Views
yipingwang
NXP TechSupport
NXP TechSupport

Hello Hymalai,

Please check DDRx_CSn_CONFIG, whether the mode "Interleaving between 2 memory controllers" is configured.

If yes, please modify DDR controller configuration in the init file, you could refer to P4080RM for the details.


Have a great day,
Yiping

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 Kudos
167 Views
hymalaibello
Contributor III

Hi!

This is a resume of the Init-core

#LAW31 to DDR - 2GB

mem [CCSR 0xDF0] = 0x00000000

mem [CCSR 0xDF4] = 0x00000000

# Interleaved mode

mem [CCSR 0xDF8] = 0x8140001E


# DDR1_DDR_SDRAM_CFG

mem [CCSR 0x8110] = 0x470C0000

# DDR1_CS0_CONFIG

mem [CCSR 0x8080] = 0x80014202 # Interleaving Disable

# DDR1_CS1_CONFIG

mem [CCSR 0x8084] = 0x80014202

# DDR1_CS2_CONFIG

mem [CCSR 0x8088] = 0x80014202

# DDR1_CS3_CONFIG

mem [CCSR 0x808C] = 0x80014202


# DDR1_CS0_BNDS

mem [CCSR 0x8000] = 0x0000001f

# DDR1_CS1_BNDS

mem [CCSR 0x8008] = 0x0020003f

# DDR1_CS2_BNDS

mem [CCSR 0x8010] = 0x0040005F

# DDR1_CS3_BNDS

mem [CCSR 0x8018] = 0x0060007F



# DDR1_DDR_SDRAM_CFG

mem [CCSR 0x8110] = 0xC70C0000 

# DDR2_DDR_SDRAM_CFG

mem [CCSR 0x9110] = 0xC70C0000


the same configuration is done for DDR2

And when I debug, I cannot run the main.

Screenshot.png


Thanks!


Regards,


Hymalai Bello


0 Kudos
168 Views
yipingwang
NXP TechSupport
NXP TechSupport

Hello Hymalai,


I received your initialization file.


1. For DDR controllers without interleaving.

a. define separate LAWs(done)

b. DDR controller registers configuration

CS0_BNDS

Differnet bank for both controllers, for example MC1:CS0_BNDS 0x0000001F MC2:CS0_BNDS 0x0060007F

DDRx_CSn_CONFIG[INTLV_EN] diabled(done)

DDRx_DDR_SDRAM_CFG[BA_INTLV_CTL] disabled(done)



2. As your description previously, you said you wanted to use CPC as SRAM and DDR together, but I didn't find you allocate LAW for SRAM in the initialization file.

In the initialization file, if the SRAM is not needed, please don't allocate TLB entries for it (TLB14 and TLB15).

If you want to use SRAM, please make sure the address allocation is not overlapped with DDR.


You didn't mentioned what problem you encountered, please feel free to let me know if the problem remains.


Have a great day,
Yiping

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

View solution in original post

167 Views
hymalaibello
Contributor III

Hi!

Can I use the registers for  Partition allocation of CPC (CPC1_CPCPAR1....) when I am using CPC as SRAM?  Is for assign  a private space to each core.

thanks!

Regards,

Hymalai Bello

0 Kudos
167 Views
yipingwang
NXP TechSupport
NXP TechSupport

Hello Hymalai,

For LAW configuration, please configure LAW_LAWARn[TRGT_ID] configuration as "0x10" or "0x11" as DDR controller 1 or DDR controller 2, and define separate LAWs for DDR controller 1 and DDR controller 2.

0x10 Reserved Memory Complex 1       DDR controller 1 or CPC1 SRAM

0x11 Reserved Memory Complex 2        DDR controller 2 or CPC2 SRAM

0x14 Reserved Interleaved Memory Complex 1/2      Interleaved DDR controllers or CPC SRAM.

If you problem remains, you could send your CodeWarrior sample project to me through email directly.


Have a great day,
Yiping

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 Kudos