Initialization (.cfg) file by using CW and CW-TAP

[esode]

Hello all,

I am using CW to bring up the P2010 chip on a custom board.

I am using a target initialization file (.cfg file) and the first lines of the file are:

writemem.l 0xFF720000 0xB0010000 #enable L2 as SRAM

writemem.l 0xFF720100 0xFFF00000 #set L2 SR BAR

writemem.l 0xFFFFF000 0x48000000 #instruction at debug interrupt

writemem.l 0xFFFFF700 0x48000000 #instruction at program interrupt

writemem.l 0xFFFFFFFC 0x48000000 #instruction at reset vector

# set interrupt vectors

writereg IVPR 0xFFFF0000 # IVPR (pointing to L2 SRAM location)

writereg IVOR15 0x0000F000 # debug - (a valid instruction should exist to be fetched)

writereg IVOR6 0x0000F700 # program

#######################################################################

# Set a breakpoint at the reset address

writereg IAC1 0xfffffffc

writereg DBCR0 0x40800000

writereg DBCR1 0x00000000

writereg MSR 0x02000200

writemem.l 0xFF701010 0x03010000 #enable CPU0 and CPU1

run

sleep 0x10

stop

I have enabled the CCS logging in the CW and the error-output is:

ccs_write_mem

  coreh = [serverh:0;cc_index:0;chain_pos:0]

  addr = [space:0;size:4;address:0xff720000]

  data: (size = 4)

  B0010000

  ccs_write_mem; ccs_error = -2147483641; duration=30 ms

  Error message: SAP error

It seems that the error is occurred at the first line of the .cfg file. CW and CW-TAP cannot execute the writemem.l command in the .cfg file.

I would appreciate any idea/clue about the problem. My jtag chain file configuration is

P2010 (2 0)

Generic 10 1 0x3FF

Generic  8 1 0xFF

[esode]

I attached the log of the ccs command in the CW. Please take a look at the .txt file.

[marius_grigoras]

Hi,

I just took a look on the log file and it seems that you're getting a SAP error just at the first read_mem access (this is after reset procedure).

It seems to be a problem with config_chain; I have 2 questions here:

1. Are you sure that the DIP SW settings are for P2010 personality and not for P2020?

2. Are you sure that you're using a P2010 project and not a P2020 one?

Thank you,

Marius

[esode]

Yes, you are right about the SAP error when first reading. Here are my answers:

1) Our board is custom board, not a FreeScale demo board. And, we are sure that JTAG configuration is correct in CW.

And,  by looking the log file you may see that CW finds 3 chips(one of them is p2010) on the jtag chain.

2) Yes, I am sure that I create my project for p2010 when using CW's new project wizard. It is a bare metal project.

Sincerely,

[marius_grigoras]

Ok, now I understand. CodeWarrior doen't support any custom board for a specific processor.

So, you tried with the sram init file as Yiping suggested above? It's the only way to get rid of this SAP error.

Secondly, you can try to use the DDR Validation 1.3.0 (this is a powerful tool that can be used with CW and PEx for finding your custom DDR settings).

Regards,

Marius

[esode]

Actually I used CW and gdb to bring up the P2010 on our board.

The gdb works now after Freescale provided a new firmfare for the TAP for P2010 and init.gdb files for p2010. I can initialize and execute a .elf file on the P2010 now. This shows us that our board is ok as hardware.

However, there is still problem on CW side. I open a project for the same board and I only try to connect to the p2010.

Then, I debug; I see that I can read/write on the core registers, however there is a problem for  memory mapped registers. Those registers are not reachable. I opened a ccs log on CW and generally we get this error:

"Error message: cannot start SAP transaction".

CW version is 10.3. And I think the TAP version is below:

(bin) 61 % show cc

0: CodeWarrior TAP (cwtap:192.168.1.131) CC software ver. {0.0}

[esode]

The CWTAP version is here:

(bin) 61 % show version

CCS Linux Release Build 365p0

CodeWarrior Connection Server version {4.13}

(C) Copyright 2003-2010 Freescale Semiconductor, Inc. ALL RIGHTS RESERVED

[yipingwang]

Please refer to <CodeWarrior install folder>\PowerPC_EABI_Support\Initialization_Files\QorIQ_P2\P2010DS_init_sram_flash.cfg.

[marius_grigoras]

Hi,

What CW and CW-TAP versions are you using?

Regards,

Marius

[lunminliang]

Maybe you can check your pin status during reset according to Hardware Specification document including footnote. Also, you seem to write a reserved value into L2CTL[L2SIZ] field, I am not sure whether this will affect, try to change the value from "B0010000" to "A0010000".

[esode]

Actually, in our earlier steps, some problems were due to hardware. I believe that we solved hardware related problems. Because, we can bring up the chip(p2010) by using gdb debugging tools.