Since you don't know anything about the state of cores 1-7, it's possible that they could be actively interfering with core 0 or otherwise causing trouble. In general this isn't a situation that we support recovering from.
Also note that if core 1-7 have modified memory that core 0 is interested in, that memory may still be in the cache of core 1-7 and the modifications will be lost when you reset the cores.
But if you want to try, or can put some bounds on the state of cores 1-7:
1. Make sure no core is in a low power state (using the RCPM registers, and make sure no core re-enters low power state after core 0 pulls them out).
2. Reset cores 1-7 using MPIC_PIR and the sequence documented in section 22.3.11 "
Processor initialization register (MPIC_PIR)" of the P4080 reference manual.
3. Set up the boot page mapping to point to the code you want the cores to run.
4. Release the cores from holdoff using CONFIG_BRR.
Note that at this point the timebase will not be synchronized across cores. You can synchronize them by disabling the timebase for all cores using RCPM_TBENR, setting the timebase to the same value on all cores, and then enabling all the timebases at once using RCPM_TBENR.
