I'm attempting to build a u-boot version for P1022 that will boot into SRAM, so that it can discover and configure any installed DIMM. I'm concerned that the standard boot file (config_ddr3_2gb_p1022ds.dat) won't work reliably on a machine fitted with a smaller or slower DIMM.
I've found and fixed the following problems, but there are more remaining. Has anybody got a configuration like this to work?
1. The config_sram_p1022ds.dat file sets the boot vector to f8f80000, rather than f8fff000 used in config_sram_p2020ds.dat
2. The u-boot config file for the P1022DS in SD boot mode sets TEXT_BASE to 0x11000000, rather than the 0xf8f80000 used in P2020DS.h
My config file:
040:424f4f54 Boot signature
044:00000000
048:00080000 Image size - should be overridden by boot-format
04c:00000000
050:00001000 Image location on SD card - should be overridden by boot-format
054:00000000
058:f8f80000 RAM address of image
05c:00000000
060:f8fff000 Start vector
064:00000000
068:00000006 Config size
080:ff720100 Set L2SRAM to f8f80000
084:f8f80000
088:ff720e44 Disable L2 cache ECC errors
08c:0000000c
090:ff720000 Enable L2 as all SRAM
094:80010000
098:ff72e40c Set RD_SAFE on SDHC controller
09c:00000040
0a0:40000001 Delay 0x100 instruction
0a4:00000100
0a8:80000001 End configuration
0ac:80000001
My modified u-boot config section:
#ifdef CONFIG_SDCARD
#define CONFIG_RAMBOOT_SDCARD
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_SYS_TEXT_BASE 0xf8f80000
#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
#endif
Solved! Go to Solution.
L2 Cache size of P1022 is 256K, but P2020's is 512K, P1022 L2 Cache for SRAM cannot accommodate the whole u-boot Image.
L2 Cache size of P1022 is 256K, but P2020's is 512K, P1022 L2 Cache for SRAM cannot accommodate the whole u-boot Image.
Thanks - I've had a go at trimming out u-boot features, but I can't get one small enough that's useful in my environment.
t looks like I'll need to get the SPL support working for SD card booting.
Have a look at the controlcenterd_TRAILBLAZER board configuration. It's a trimmed u-boot configuration (not SPL) that does what you asked for.
This is our config file for booting to SRAM:
40:424f4f54
44:00000000
48:00040000
4c:00000000
50:00000400
54:00000000
58:f8fc0000
5c:00000000
60:f8fff000
64:00000000
68:00000006
80:ff720100
84:f8fc0000
88:ff720e44
8c:0000000c
90:ff720000
94:80010000
98:ff72e40c
9c:00000040
a0:40000001
a4:00000100
a8:80000001
ac:80000001
Check out the latest upstream U-Boot (especially commit 7c8eea59b8c3b124d23b41f887bc525cf2adec30), which supports SPL for SD on P1022DS, with DDR SPD support.
Please refer to P2020DS.h to add L2 Cache configuration as the following.
#define CONFIG_SYS_INIT_L2_ADDR>>---0xf8f80000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_L2_ADDR_PHYS>---0xff8f80000ull
#else
#define CONFIG_SYS_INIT_L2_ADDR_PHYS>---CONFIG_SYS_INIT_L2_ADDR
#endif
#define CONFIG_SYS_L2_SIZE>->---(512 << 10)
#define CONFIG_SYS_INIT_L2_END>-(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SYS_CCSRBAR>->---0xffe00000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW>CONFIG_SYS_CCSRBAR