How to access GPIO's in P1021 processor?

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How to access GPIO's in P1021 processor?

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sourabhdas
Contributor III

Hello everyone,

I am using P1021 processor in my project. I am using QorIQ SDK - 1.7. I have gone through the P1021 Reference Manual provided by the freescale but I am not clear with the GPIO base and offset addresses.

Is there any macros defined for the GPIO pins in the QorIQ SDK source code, so that they could be accessed directly through the API's?

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Pavel
NXP TechSupport
NXP TechSupport

Freescale SDK supports sysfs possibility for GPIO using from user space.

Check please that the following kernel configuration options are set. These options are necessary

for sysfs GPIO support:

CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB

CONFIG_MPC8XXX_GPIO (Platform Support / MPC8xxx GPIO support)

CONFIG_OF_GPIO

CONFIG_GPIOLIB (-*- GPIO Support  --->  )

CONFIG_GPIO_SYSFS (/sys/class/gpio/... (sysfs interface))

CONFIG_GENERIC_GPIO

This option can be checked using the .config file in the kernel source folder.

GPIO controllers should be declared in the Device Tree file.

More information on the device tree GPIO declaration can be found in the kernel source.

See please the following files:

/Documentation/powerpc/dts-bindings/gpio.txt and /Documentation/powerpc/dts-bindings/fsl/8xxx_gpio.txt

This possibility is available using sysfs from user space.

See the following pages

(http://elinux.org/GPIO)

and

(https://www.kernel.org/doc/Documentation/gpio/sysfs.txt).

and

(http://www.lindusembedded.com/blog/2011/12/29/gpio-general-purpose-inputoutput-interfaces-in-linux-2...)

and

(https://www.kernel.org/doc/Documentation/gpio/sysfs.txt).

Attached file contains .dts file and command dump for GPIO using.

The second method consist of using mmap command.

It is a POSIX-compliant Linux/Unix system call that maps files or devices into memory.

It is a method of memory-mapped file I/O.

For example, look at the following links (http://en.wikipedia.org/wiki/Mmap) and

(http://beej.us/guide/bgipc/output/html/multipage/mmap.html).


Have a great day,
Pavel

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lunminliang
NXP Employee
NXP Employee

Hello Sourabh Das,

GPIO base and offset address as below:

GUTS_CPODRn    E_0000h base + 100h offset + (32d × i), where i=0d to 2d

GUTS_CPDATn      E_0000h base + 104h offset + (32d × i), where i=0d to 2d

GUTS_CPDIR1n    E_0000h base + 108h offset + (32d × i), where i=0d to 2d

GUTS_CPDIR2n    E_0000h base + 10Ch offset + (32d × i), where i=0d to 2d

GUTS_CPPAR1n    E_0000h base + 110h offset + (32d × i), where i=0d to 2d

GUTS_CPPAR2n    E_0000h base + 114h offset + (32d × i), where i=0d to 2d    

This is described in Section 20.5 GUITS Memory Map/Register Definition of P1021RM.pdf Rev. 6.

And this is the example in p1021rdb-pc_32b.dts

soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;

par_io@e0100 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xe0100 0x60>;
ranges = <0x0 0xe0100 0x60>;
device_type = "par_io";
num-ports = <3>;

qe_pio_b: gpio-controller@20 {
#gpio-cells = <2>;
compatible = "fsl,mpc8569-qe-pario-bank",
"fsl,mpc8323-qe-pario-bank";
reg = <0x20 0x18>;
gpio-controller;
};


Have a great day,
Lunmin

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