Hardware Signal Ambiguity - cfg_rcw_src(0:4), most significant bit?

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Hardware Signal Ambiguity - cfg_rcw_src(0:4), most significant bit?

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bobkorkuc
Contributor I

I am a hardware engineer and am confused by how to associate the cfg_rcw_scr(0:4) to the actual Hardware Signals. The confusion results in not being able to determine the most significant bit for the cfg_rcw_scr bits.


For the hard coded table shown above, Table 4-32, for a 1_0010 equating to cfg_rcw_src(0:4), what is the most significant bit, cfg_rcw_src[0] or cfg_rcw_src[4]?


For the LGPLx hardware signals shown below, it is ambiguous which is the msb when you write cfg_rcw_src(0:4) = 1_0010. Hardware convention suggests that the left most digit is the msb and it is cfg_rcw_src(0).

 

Cfg_rcw_src[0] = LGPL0

 

Cfg_rcw_src[1] = LGPL1

 

Cfg_rcw_src[2] = LGPL2

 

Cfg_rcw_src[3] = LGPL3

 

Cfg_rcw_src[4] = LGPL5

 


Can someone clarify the ambiguity?


Thanks,


Bob

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LPP
NXP TechSupport
NXP TechSupport

In the expression "cfg_rcw_src(0:4) = 1_0010", the bit sequence is the same on the left and right sides.

I.e. cfg_rcw_src[0] = 1 and cfg_rcw_src[4] = 0.


Have a great day,
Pavel

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