Embedded ISP possibility for QorIQ

[azdem]

Hello Experts,

we are using a P2010 without any directly connected non-volatile storage. So, we need to load the program code (not a Linux kernel, just bare-metal, without OS) to the external SRAM, connected to the P2010 local bus, right after power on. Currently, gdb can do the basic initializations and load the program code to the SRAM utilizing a CW-TAP as bridge from PC to the P2010 JTAG interface. We want to implement this basic functionality (without debug capabilities) to our end product, so that our embedded Linux processor (probably ARM) can do this autonomously without PC. Freescale offers the binaries (gdb proxy & ccs) that run on CW-TAP ARM processor, which translate the gdb operations to JTAG interface. CCS seems to have an API. Are they somehow usable? How difficult would it be to implement this basic functionality over the debug channel? Should I invest time in this task or should I try simple & slow boundary scan bit banging to load code to SRAM?

Regards,

A.D.

[azdem]

Can anyone please help?

[sinanakman]

Hi Azdem, I am not an expert on CW-TAP but I work with JTAG debuggers.

It is not exactly clear what you are trying to do. Do you need to load

the program code to SRAM without using CW-TAP but still via the JTAG

port ?

You also ask if you should try simple boundary scan bit banging : I don't

think you should take this avenue. A simple bit banging will not get you

communicate with your P2010s TAP. Accessing memory via DAP needs more

complex sequence then what a simple bit banging would probably achieve.

You would need to use a JTAG probe that supports this SoC.

The other alternative is of course to have a small pre-loader in your flash and that

loads your program code to sram after initializing it. This is probably something you

already considered but perhaps you don't have any flash memory in your design.

Hope this gives some insight.

Sinan Akman

[azdem]

Hi Sinan,

thanks for your answer.

Yes, I want that my Linux processor manages the JTAG interface of P2010 via GPIO on its own and load data to the external SRAM connected to the P2010 local bus. If it does not use the boundary scan, first it had to take control of the debug core of P2010 and set a few register correctly that the local bus interface gets ready. That's the fast & complicated way.

Using standard boundary scan feature of JTAG, I can, read/write each pin of the processor. In that way, I can load data to the "externally" connected SRAM, without fiddling with internal debug core of P2010. But, it will be very slow, because I need to shift over 600 bits (for each pin) in order to toggle the pseudo-local bus interface once.

Regards,

A.D.