Please look P1010 Reference Manual, Figure 9-1. All interrupt sources are signaled to the core through the same "int" input. That is, from the core point of view, all interrupts have the same entry point, and every "int" assertion jumps to this point. Then this interrupt handler is called, the core have to do something with external "int" request to clear it, so it may be asserted again to call interrupt handler again for higher-priority interrupt. To clear "int" request, the core should read IACK. Reading IACK returns interrupt vector to process, and also clears external "int" request to the core, to the interrupt controller can assert it once again, if higher-priority interrupt is pending. In addition to clear "int", you should also enable back "int" recognition by the core. When the "int" is asserted and core takes interrupt, it clears MSR[EE], so further assertion of "int" is ignored. This is done to prevent re-entrance to the same interrupt handler and loosing context, because subsequent interrupt may overwrite state registers. After the state of all required state registers is saved, and processor state becomes safe for re-entering the same interrupt handled, you can enable back "int" recognition by the core by setting MSR[EE].
Have a great day,
Alexander,
TIC
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