In your case, DMA with length of 16 bytes is performed as single-beat teansaction. If you configure more than 32 bytes then burst transactions can be issued.
You can verify this supposition by disabling burst transfers by setting ORn[BI].
Please, refer to P1020RM 12.4.4.1.1 "Memory access requests"
UPM executes single-beat or burst patterns (when BI=0) based on the attributes of original CSB transaction. If BI=1 then burst patterns are never used.
DMA automatically switches between single-beat and burst modes depending on the address alignment and DMA size.
The algorithm is shown in RM Figure 13-95. DMA initiates burst if the address is 32B aligned and block size is >=32. Otherwise, single beat transactions are issued.
My opinion is that you use wrong UPM RAM pattern for burst transactions (offset RBS,WBS). Please check that it provides correct number of UTA bits, so that, total size is 32 bytes: 8 bit device should use patterns with 32 entries UTA=1, 16 bit devices should use patterns with 16 entries UTA=1.
"The user must ensure that patterns for single-beat transfers contain one, and only one,
transfer acknowledge (UTA bit in RAM word set high) and for a burst transfer, contain
the exact number of transfer acknowledges required."
Have a great day,
Pavel
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