Card synchronization in P1010 eSDHC driver multiblock transfers

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Card synchronization in P1010 eSDHC driver multiblock transfers

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aleksander
Contributor I

hello!

I am implementing multiblock transfers in P1010 eSDHC driver in FreeBSD. The driver already uses SDMA with single block transfers.

The thing is, performing a multiblock write causes Command Timeout (read worked fine). The driver is always waiting for DAT and CMD line (I know I don't always have to wait for DAT line) reading PRSSTAT[CIHB, CDIHB, WTA, RTA], but that seems to be not enough - the driver is only working fine, when I have some debug printf's in interrupt_handler.

I suppose that I am sending next command before card copy the data from its internal buffer to the card, and thats why CMD Timeout is generated, but how to synchronise it, if PRSSTAT doesn't work? Watermark Level Register is also set to perform slowest transfer.

The code is in attachment.

regards

Aleksander

Original Attachment has been moved to: fsl_sdhc.c.zip

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lunminliang
NXP Employee
NXP Employee

If the DMA/CPU does not keep up with reading data out of the buffers, SDHC stops the SD_CLK at the block gap to avoid an overflow situation.


The block size can be a multiple of the size of the data buffer. However, it is recommended that the block size be equal to the data buffer size. This allows the SDHC to stop the SD_CLK during block gaps should an overflow or underrun condition occur. Stopping the SD_CLK while the data lines are active may cause data corruption on some cards. If an application or card driver needs to transfer larger sets of data, the host driver should divide the data set into multiple blocks.

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lunminliang
NXP Employee
NXP Employee

See please attached file. This file contains SDHC driver code from Freescale SDK 1.3.2 (http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=SDKLINUX&fsrch=1).

Compare this driver and your code.


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rautaioan-alin
Contributor I

Hi, A D !

How did you solve your issue ?

Because I'm running into something similar on p1024rdb and I can't get 2 consecutive multiple block writes working ...

Any suggestion would be useful.

Thank you in advance,

Alin

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aleksander
Contributor I

and related question - what is "stop at block gap" functionality? I don't understand it, and google lacks of answer. should I use it?

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lunminliang
NXP Employee
NXP Employee

If the DMA/CPU does not keep up with reading data out of the buffers, SDHC stops the SD_CLK at the block gap to avoid an overflow situation.


The block size can be a multiple of the size of the data buffer. However, it is recommended that the block size be equal to the data buffer size. This allows the SDHC to stop the SD_CLK during block gaps should an overflow or underrun condition occur. Stopping the SD_CLK while the data lines are active may cause data corruption on some cards. If an application or card driver needs to transfer larger sets of data, the host driver should divide the data set into multiple blocks.

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