CPLD update using JTAG in P1022 processor

[hemwant]

We are trying to update (lattice) CPLD in our P1022 board using JTAG . In this mode Processor GPIO's are configured as TMS, TCK, TDi, TDO respectively and Cpld is updated using vme file.

The toggling of TCK pin(GPIO) doesn't generate required frequency of 25 Mhz , for now using memory map to get and set GPIO . Please suggest fastest mode of accessing GPIO's in P1022 board as it shows frequency error.

Note:- The same method of CPLD update using jtag is working in 8260 board.

[ufedor]

TCK, TDO, TMS should be configured as push-pull outputs.

TDI should be configured as input.

[ufedor]

You wrote:
> required frequency of 25 Mhz
Why you think that there should be "required" frequency? - 25 MHz is maximum supported TCK frequency.

JTAG interface implementation is static and could operate at any TCK frequency.

The fastest mode of gpio accessing can be implemented using assembler code.

Which method is used currently?  

[hemwant]

ufedor‌

The code was unable to read vendor id , whereas individual gpio were probed when they were actively driven.

As a result we had doubt regarding clock frequency.

We are accessing GPIO using their  mapping in the virtual address space and  reading the GPIO using their 32 bit address.

The configuration of pins is done as follows-

1) Open drain all 4 JTAG signal.

2) Assigning respective direction to GPIO signal

3) Lastly all 4 pins are set in high state (value 1 in data register of GPIO)

[ufedor]

It is required to verify that JTAG signals in the code are correctly mapped to the GPIO pins.

[hemwant]

Jtag signals are correctly mapped to GPIO pins as when we toggle the GPIO's same can be probed using multimeter.

The configuration of pins is done as follows-

1) Open drain all 4 JTAG signal.

2) Assigning respective direction to GPIO signal

3) Lastly all 4 pins are set in high state (value 1 in data register of GPIO)

Is the above configuration correct to configure GPIO as jtag?