I am writing a routine for disabling an already enabled CPC. When I try to flush CPC during this course, set number 0 to 255 of the cache get flushed, but set number 256 to 511 do not get flushed.
I am using the method specified in P4080DS Reference Manual for disabling CPC:
a) Reset all CPCPARn registers
b) Set CPCFL in CPCCSR0 register
c) Wait for CPCFL to be reset by hardware
d) Clear locks by setting CPCLFC and wait for it to be reset by h/w.
e) Disable the CPC using CPCE bit.
Am I missing something or is there an errata related to this?
If software wishes to flush the cache after it has been enabled, it must do the following:
1. Clear all bits in CPCPAR0–15 to prevent any transaction from allocating in the CPC
2. Perform a dcbf operation to each coherency granule mapped to the memory target (that is, one dcbf for each 64 bytes).
Please find more details in the corresponding Technical Case.
Thanks for your answer.
I tried flushing using dcbf, but it could not flush the lines from L3 cache. When I referred the EREF manual, it says dcbf flushes caches local to the core. It flushes external caches only if target memory address is mapped with M (Memory Coherence) bit set.
Let me provide the context I am working in:
I am loading a bareboard software using Uboot.
I want to flush and disable L3 cache before doing anything else in bareboard software.
SInce Uboot has not mapped the memory with 'M' bit set, dcbf doesn't seem to work on L3 cache.
Also, I could not find any way to answer on comments made in the corresponding technical case. Is there a way to do that?