Hi,
As i was reconfigurating the DDR on a default codewarrior project i came up with à little problem.
In the default configuration, the DDR(interleaved controllers) is mapped from 0x0000_0000 to 0x7FFF_FFFF.
What I did was to remap the DDR from 0x0000_0000 to 0x3FFF_FFFF (which is 1GB or 512MB per controller)
I also disabled the interleaving mode which means each DDR controller is assigned 512MB of space (DDR1 from 0x0000_0000 to 0x1FFF_FFFF and DDR2 from 0x2000_0000 to 0x3FFF_FFFF)
The code start addresses were changed in the .lcf file according to the new DDR mapping. DDR1 unchanged but DDR2 changed from 0x40XX_XXXX to 0x20XX_XXXX (code, heap and stack, etc.)
When i run the default main(), core1 is stuck at adresse 0x...X_4000_0700 when executing asm("sc;"), command.
When I run the project without the asm("sc";); command on core1 it works fine. (the command does work on core0 because it jumps to adress 0x...X_0000_0700)
Does any one know what is missing to make it work ?
Thanks
已解决! 转到解答。
Hi,
First thanks for responding marius.
So yes this is what I have in the lcf file.
But I have just found the solution and every thing works.
The problem was the interupt vector address.
In the .tcl file you have :
if {$Ret} { | |
reg ${SPR_GROUP}IVPR = 0x[expr {${proc_id} << 2}]0000000 |
} else {
# SMP project, same interrupt vectors for all cores | |
reg ${SPR_GROUP}IVPR = 0x00000000 |
}
whick means that for core1, proc_id = 1 then left shift of 2 bits multiplies it by 4 so we end up with 0x4000_0000.
But the DDR was remapped and consequently the code was displaced to 0x2000_0000 for core 1.
So I had to change the 2 by a 1 which makes a shif of 1 bit and so on multiplies the proc_id value (1) by 2 and we end up with 0x2000_0000.
So here is the correct tcl code :
if {$Ret} { | |
reg ${SPR_GROUP}IVPR = 0x[expr {${proc_id} << 1}]0000000 |
} else {
# SMP project, same interrupt vectors for all cores | |
reg ${SPR_GROUP}IVPR = 0x00000000 |
}
cheers.
Hi,
So, you updated the lcf file for the second core, right?
You'll need to have something like this:
_stack_addr = 0x203dfff0;
_stack_end = 0x203d7ff0;
_heap_addr = 0x203cfff0;
_heap_end = 0x203d7ff0;
.intvec 0x20000000 :
{
*(.intvec)
} = 0xffff
. = 0x20100000;
.newstart :
{
*(.newstart)
}
/* the rest of the file */
If this still doesn't work, please make some hardware diagnostics for DDR (right click in the target task view).
Regards,
Marius
Hi,
First thanks for responding marius.
So yes this is what I have in the lcf file.
But I have just found the solution and every thing works.
The problem was the interupt vector address.
In the .tcl file you have :
if {$Ret} { | |
reg ${SPR_GROUP}IVPR = 0x[expr {${proc_id} << 2}]0000000 |
} else {
# SMP project, same interrupt vectors for all cores | |
reg ${SPR_GROUP}IVPR = 0x00000000 |
}
whick means that for core1, proc_id = 1 then left shift of 2 bits multiplies it by 4 so we end up with 0x4000_0000.
But the DDR was remapped and consequently the code was displaced to 0x2000_0000 for core 1.
So I had to change the 2 by a 1 which makes a shif of 1 bit and so on multiplies the proc_id value (1) by 2 and we end up with 0x2000_0000.
So here is the correct tcl code :
if {$Ret} { | |
reg ${SPR_GROUP}IVPR = 0x[expr {${proc_id} << 1}]0000000 |
} else {
# SMP project, same interrupt vectors for all cores | |
reg ${SPR_GROUP}IVPR = 0x00000000 |
}
cheers.