Alternative method to disable the level 2 & 3 caches.

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Alternative method to disable the level 2 & 3 caches.

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vasanthsri
Contributor III

Hello Experts,

Is there any approach available (like uboot configuration parameter, etc..) to disable level 2 and level 3 caches on e500mc platform ?

I can think of L2E bit of L2CSR0 register, but looking for something as in part of boot time itself .. In parallel, searching surfing for the code (linux) where these caches are booted (init sequence) and also not sure how safe it is to comment (remove) those cache init/powerup code.


And also, if we disable the L2 cache using L2E bit (-> 0), is there any alternative method  available to verify the status of L2 cache(on/off) other than checking this bit status ?


Thanks in Advance.

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scottwood
NXP Employee
NXP Employee

There is no special way to disable L2 other than modifying U-Boot code to not set L2E.  Likewise for verifying the state of L2 -- just check the bit in the register.

For CPC (L3), you can set "en_cpc:" in the U_Boot hwconfig variable to control which (if any) CPCs are enabled.

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vasanthsri
Contributor III

Thanks Scott for providing this option.

CPU0:  P4080E, Version: 3.0, (0x82080030)

Core:  E500MC, Version: 3.1, (0x80230031)

Clock Configuration:

      CPU0:1500 MHz, CPU1:1500 MHz, CPU2:1500 MHz, CPU3:1500 MHz,

      CPU4:1500 MHz, CPU5:1500 MHz, CPU6:1500 MHz, CPU7:1500 MHz,

      CCB:800  MHz,

      DDR:650  MHz (1300 MT/s data rate) (Asynchronous), LBC:25  MHz

      FMAN1: 600 MHz

      FMAN2: 600 MHz

      PME:  600 MHz

L1:    D-cache 32 kB enabled

      I-cache 32 kB enabled

Board: P4080D (36-bit Addressing)

      Workaround for A-004510: Disabled

      HW-config: en_cpc

I2C:  ready

DRAM:  Initializing....

ctrl 0: freq=1300MHz, 1 ranks

ctrl 1: freq=1300MHz, 1 ranks

DDR3: Checking persistent memory .. OK

Contiguous memory option set

Detected 8192 MB of memory

    DDR:  2 GB (DDR3, 64-bit, CL=9, ECC on)

Glue Logic FPGA Version: 0x003b

Terminal server is alive

L2:    128 KB enabled

Corenet Platform Cache: 2048 KB enabled

Using SERDES configuration 0x1d, lane settings:

SERDES: bank 2 disabled

Bank1: PCIE1 NA PCIE3 PCIE3 SGMII_FM2 SRIO2 SGMII_FM2 SRIO1 DEBUG DEBUG

Also tried something like "HW-config: en_cpc:cpc6,cpc7;" and observed same logs like above .

I thought, the CPC enabled message will not appear after setting the HW config bit, but though the "en_cpc" bit is enabled (highlighted in Blue), U-boot is still printing the message that CPC is enabled ?

Does this mean CPC is disabled but this message is sort of generic irrespective of hwconfig status ?

Thanks.

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scottwood
NXP Employee
NXP Employee

You trimmed the U-Boot output that shows what version you're using...  It looks like en_cpc is supported in recent upstream U-Boot, as well as the U-Boot in SDK 1.5 -- but for some reason, it is not in the U-Boot in SDK 1.6.

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