NXP advertises 3 MIPs/MHz - what toolchain and options were used to achieve this performance?
Thanks,
Have a great day,
Originally they use GCC 4.5.1 compiler and compile Dhrystone version V2.1 with optimization level O2. If you need more details please create technical case - refer the following link:
https://community.freescale.com/thread/381898
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I am only getting 1.8 MIPs/MHz on a P5020DS using GCC 4.7.2 (CodeWarrior) w/ -O3.
I will open a support request.