I have a P4080DS board ,we have two questions about DDR Memory Controller register:
1. about 11.4.9 DDR SDRAM control configuration 2
in this regiser bit24-25 is reserved ,but when I set bit 24 -25 as 00,it doesn't work;when
I set bit 24-25 as 01 ,it work well.can you tell me why?
2.about 11.4.10 DDR SDRAM mode configuration
(DDRx_DDR_SDRAM_MODE) and 11.4.11 DDR SDRAM mode configuration 2
these two registers are very important for different DDR rate,but I don't know how to config them in different DDR rate, the P4080RM didn't give us a detail explain ,Please give us more detail information about these two registers.Thank u very much!!
1. Probably some other registers are set incorrectly. This mainly concerns DDRx_DDR_SDRAM_CFG and DDRx_DDR_SDRAM_MODE registers.
2. Those registers are used to set SDRAM's Mode registers MR0.. MR3. Take a look at a DDR3 data sheet for description of those registers. You can also look at AN4039 app note, it provides DDR_SDRAM_MODE and DDR_SDRAM_MODE_2 fields description.
we found the describtion of DDRx_DDR_SDRAM_CFG and DDRx_DDR_SDRAM_MODE registers,but we can't config these registers
many bits describe like this "
|the value in this field should match the value of TIMING_CFG_X[X]"|
we don't know how to match the value ,for example:
|The value in this field must match the CAS latency programmed in TIMING_CFG_1. The|
DRAM data sheet should be consulted to select the proper CAS latency value.
how to match the value？
2.bits 20-22 SDMODE[WR]：
|Regardless of the value of DDR_SDRAM_CFG_2[OBC_CFG], the value of this bit|
should be based on the tWR obtained from the DRAM data sheet. When
DDR_SDRAM_CFG_2[OBC_CFG] = 0, the value in this field should match the value of
TIMING_CFG_1[WRREC]. But when DDR_SDRAM_CFG_2[OBC_CFG] = 1, the value
in this field is two clock cycles value less than the value of TIMING_CFG_1[WRREC]
in this register there is only 3 bits but there are 4 bits in TIMING_CFG_1[WRREC], how to match these two values?
and so on,there are too much describtion like this,Please tell me how to match these registers detail,thanks
1. CAS latency is defined by the SDRAM data rate. For example, for 1200MT/s CASLAT can be set to 8 clocks. This should be set in both, SDRAM's MR0, (DDR_SDRAM_MODE's bits 25-27, 29 = 1000) and TIMING_CFG_1 (bits 12-15 =1111).
2. We recommend to set DDR_SDRAM_CFG_2[OBC_CFG]=0, this simplifies your problem. This also requires following settings: DDR_SDRAM_CFG[8_BE]=1, DDR_SDRAM_MODE[30,31]=00.
Number of bits in the registers is not important, you need to read comments. For example, if SDRAM's MR0[WR]=001, then Write_Recovery=5clk. P4080's TIMING_CFG_1[WRREC]= 0101 also corresponds to 5clk Write Recovery time.