When the frames on a FQ are ready to be processed, the FQ is enqueued onto a work queue(WQ). WQ are organized into channels. A channel is a fixed, hardware-defined association of 8 work queues, also though of “priority work queues”. There are two types of WQ channels defined in QMAN: Dedicated channels, which are always serviced by a single entity. Pool channels, which are serviced by pool of like entities, such as a pool of processor cores. This document describes the basic concept regarding dedicated and pool channels, how to use dedicated and pool channels in flow order Preservation scenarios, work queue channel assignment, dedicated and pool channel used in Linux Kernel and how to modify PPAC and USDPAA QMAN driver to using dedicated channels in USDPAA applications. 1. Basic Concept of QMAN Channels 2. Dedicated Channel Used in Flow Order Preservation Scenario 3. Pool Channel Used in Order Preservation with Hold Active Scheduling 4. Work Queue Channel Assignment 5. Dedicated and Pool Channels Usage in Linux Kernel 6. Using Dedicated Channel in USDPAA
A shared-MAC device is one that can be used from two Linux and/or USDPAA partitions. Shared-MAC net device can be used in two scenarios, two or more Linux separate partitions under control of hypervisor(topaz), one Linux and one USDPAA running in the same partition. 1. DPAA Ethernet Driver Types 2. BMan Driver for shared-MAC and MAC-less port 3. QMan Driver for shared-MAC and MAC-less port 4. Running Shared-MAC between USDPAA and Linux
In a previous document, I went through the basic steps of building SDK 1.3.2 for the first time. Now I'm ready to deploy the images onto my target, a P3041DS system. Fortunately my P3041 already has a U-boot and linux install on it. So I can just try and update the SDK from within U-boot. I boot up my trusty terminal - I use putty, and connect to my local COM port at 115200 baudrate. My Ubuntu server already has a tftp server installed, and I link my images over from the SDK build/deploy/images directory over to the /tftpboot directory. The QorIQ_SDK_Infocenter.pdf document within the install has information on the flash bank usage for the current SDK. Make sure you use the document and flash map from the current SDK, as things change. I ended up with a system that didn't boot when I used the older location for the fman uCode (from SDK 1.x) on the SDK 1.3.2 system. Here is a table from the document that shows the flash map for a couple of the QorIQ DS system. It's important to note here that this covers the NOR flash - which is what I'm currently using. You may want to experiment with using NAND or SPI based flash instead - but for my purposes I'm going to re-image NOR flash. The NOR on these development systems is banked, meaning that the most significant address line is tied to a DIP switch. So I can have multiple images in Flash at one time, and switch between them (especially helpful when I mistakenly corrupt one). I'm currently in bank0 (which is the "current bank" in the table above). From this, I see that the addresses I should be interested in are located at: Name Address rcw 0xe8000000 Linux.uImage 0xe8020000 uBoot 0xeff800000 fman uCode 0xeff40000 device tree 0xe8800000 linux rootfs 0xe9300000 To verify that this is correct, I can dump out my RCW: And I can also dump out my current U-boot (which should always start with an ASCII header identifying it): at this point I can start updating the images directly from my TFTP server. I have my tftp server already defined via the U-boot environment serverip, so I just tftp the U-boot image to a randomly picked address in RAM of 0x100000. The transfer went ok, so I can burn it into flash now. I will first erase the flash starting at 0xeff80000. Since U-boot is 0x80000 size, I'll erase from 0xeff80000 for size 0x80000. Apparently my sectors were protected. So I need to unprotect first, then erase again. And by reading the flash, I verify that it has been erased (erased NOR always reads back all 0xF's) So, now I can burn the flash: I use a binary copy. And then verify that the image was written correctly. Then we go through the same technique with the other images. I'll burn the fman ucode as well: Then for the actual images and dtb, you have an option of burning them, but I'll tftp them instead. For this I created a U-boot environment variable called ramboot, and point the image names to the paths on my server: At this point I can save the environment to flash via a saveenv command in U-boot. I'll re-boot into the new U-boot to make sure it works (if it doesn't for some reason, I can jump back to a different U-boot I had previously burned in the alternate bank, or else I'll have to use a debugger to re-burn the flash). Then, from within U-boot I can run ramboot, and if all goes well it should fetch the images and boot all the way into the new SDK. Eventually it should boot all the way to a linux prompt.
I recently pulled down SDK 1.3.2 from Freescale's SDK download site and had a chance to try and install it on a P3041DS system I have lying around. There's a lot of info in the ISO, but I thought I'd go through an initial build step by step to document what the flow is. First thing to note is that there is more than one ISO image available. I already have a Ubuntu lucid machine, that I use as a build machine. So I didn't need the virtual images. I'll need the source file - so I downloaded QorIQ_SDK_V1-3-2_SOURCE_ISO, and I am going to try this on a P3041, so I downloaded the e500mc binary. The binary isn't necessary, but it speeds up the builds significantly. When they've finished downloading, the first thing to do is mount the source ISO Within the source ISO there's an install script. I run that and let it do it's thing. Important to note that there's documentation contained within the document's directory. If you go to documents/START_HERE.html you will get html based documentation on the SDK. And, if you keep drilling down and go to documents/sdk_documentation/pdf there are some pdf documents for various features. The document QorIQ_SDK_Infocenter.pdf is a complete collection of the SDK documentation taken from the Freescale infocenter site. Once, the source is install, I do the same for the binary. Make sure you install the binary on top of the source (i.e. in the same directory). We then call the FSL poky script - which sets up the build. In this command the -m tells it what machine you're going to build to. -j indicates the number of jobs for make to spawn, and -t is how many bitbake tasks to be run in parallel. At this point I'm ready to build. I have some options for which image I want to build - I'll go with the core image, which contains some of the more common packages. So, at this point I need to make sure I'm in the build_p3041ds_release directory, and issue the command bitbake fsl-image-core which initiates the build process. When all is said and done, I can find my images in the build_p3041ds_release/tmp/demply/images directory. In my case, I have quite a few images because I've actually built the core and full images. Next, I have to grab these images and deploy them to my target.
If I don’t use the USB interface in the 4080, can I leave USBx_VDD_3P3 and USBx_VDD_1P0 pins not connected? In P4040 they are reserve with note do not connect. Can they be connected to 3.3V and 1.0V respectively? USB_VDD_1P0 must be tied to 1V or the platform voltage (based on whatever the SOC core digital power supply is). USB_VDD_3P3 can be left floating. If I don’t use USB, is it safe to leave USBx_IBIAS_REXT and USBx_VDD_1P8_DECAP unconnected? If USB is not to be used at all, keep the following USB signals floating : USB1_IBIAS_REXT, USB2_IBIAS_REXT, USB1_VDD_1P8_DECAP and USB2_VDD_1P8_DECAP, USB1_VDD_3P3, USB2_VDD_3P3.
What is requirement for the voltage ripple of DDR3 controller MVref? The nominal value of MVref is 1.5V. 1%, +/- 7.5mV is the tolerance value for MVref (ripple range). Can you please explain the RDRVR resistance for DDR3 SDRAM memory interface? RDRVR is the "Driver" resistance. It is the resistance at the driver side. Half strength is ~40 ohms and full strength is ~20 ohms. How can I determine the power rating of the resistor connected to MDIC0 and MDIC1 for both half strength and full strength? The MDIC resistors connected to MDIC [0:1] signals used for either full or half drive strength calibration do not draw much current. So you can use 1/16W rated resistors for either half or full drive calibration.
The SGMII SerDes of the 4080 can operate at either 1.25G or 2.5G. Is there a register to configure this or it just depends on the clock multipliers of the SerDes PLL? As long as you select the RCW settings for SRDS_PRTCL and the DIV and RATIO settings to select the clock speed, the SerDes registers will default to the correct value based on those RCW settings. Does P4080 SerDes in XAUI mode support 10GBase-CX4 (IEEE802.3 clause54)? In other words, are SerDes XAUI receivers and transmitters capable of communication over a 15 meter 10GBase-CX4 cable? P4080 is not designed for such long distances. An appropriate 10GBASE-CX4 PHY is needed to support such distances.
I don’t use SDHC, and we use SPI at 2.5V (CVDD=2.5V). In this case for P4080 unused SDHC pins are pulled up to 2.5V. If I want to maintain compatibility with P4040, what happens when unused SDHC pins (SDHC_DATA [0-3], SDHC_CMD) in P4040 are pulled up to 2.5V instead of 3.3V? As long as the pullup on these pins satisfies the minimum Vih of 2.0 V for a 3.3V input then this would be ok. Alternative is to pull to ground. I want to lower the CPU power consumption with make CPU frequency from 1.2GHz to 1 GHz or 800 MHz for P4080 hardware. When P4080 core is configured to be 1GHZ/ 800 MHz, what is the core’s power consumption? If you disable L2 cache, you can use 47mW/100MHz per core for lower bins. If L2 is not disabled, then you need to use 65mW/100MHz per core for the lower bin. If I don’t use SDHC, how should I connect the SDHC_DATA and SDHC_CLK? SDHC is output signal and you can leave as NC. It shouldn't matter to either pull-up or pull-down for unused SDHC interfaces. In Freescale P4080_DS schematics, the "HRST" button is connected to the LRST_B signal which is routed to the FPGA. What logic is applied to the LRST_B signal inside the FPGA, and what is the FPGA output signal connected to on the CPU? LRST is one of the Reset sources that is coming from the Pushbutton. It will cause: CPU_PORESET CPU_TRST And Peripheral_reset (PHY_RST_B, GEN_RST_B, SGMII_XAUI_SLOT_RST_B) Does access to CCSR & DCSR registers require CoreNet usage in P4080? Can a SEU single-bit error in any CoreNet register prevent further reading from internal config registers? Yes, CCSR/DCSR accesses go through CoreNet. There is no ECC on CCSR internal registers so there is no automatic scrubbing or repair that is possible. So such prevention is not possible. I have NOR Flash, NAND Flash, NVRAM and CPLD connected on eLBC with data buffer in between. All devices are in high impedance when not selected. Should the OE of data buffer be connected to GND directly or by using “AND” gate with CS0, CS1…CSn as the OE? It should be “AND”ed with all used CSn to generate the OE. This can prevent any potential data bus conflict. I do not use Secure Boot feature in my P4080 design. What should I do with Vdd_LP pin? If Secure Boot feature is not to be used, VDD_LP can be left unconnected, but should be tied to GND to reduce noise.
Usually, when I turn on the option of "reset target on launch" CW resets CPU again while connecting to CPU. With P4040, CodeWarrior (CW) does not connect to CPU when the option is on, only when I disable the option, CW can connect to CPU. What could be the problem? . "Reset target on launch" asserts HRESET to the target, thereby resetting the hardware. In most cases this is a required step, but where you don't want to assert HRESET or where your Target Initialization (.cfg) file does this for you with the "reset 1" command, you can do without this option enabled. "P10xx-P20xxRDB_P1011_jtag.txt" JTAG Configuration file is required by 8.8 CW PA for all single-core P10xx processors. Please load the “P20xxRDB_P1011_jtag.txt" JTAG Configuration file in your USB TAP configuration panel you mentioned about. 1) Set MACCFG1[Rx_Flow] && MACCFG1[Tx_Flow] to 1 2) Set RCTRL[LFC] to 1.
How can I ensure that Ethernet flow control is turned on through the register setting in P4040? Please try the below steps to enable Ethernet flow control: 1) Set MACCFG1[Rx_Flow] && MACCFG1[Tx_Flow] to 1 2) Set RCTRL[LFC] to 1. Setting the flow control bits Rx_Flow and Tx_Flow means that the MAC can detect and act on PAUSE flow control frames, receive and transmit respectively. There are two ways you can confirm or see them in action: 1) Software sending a PAUSE frame through TCTRL[TFC_PAUSE] 2) Changing some hidden FIFO threshold registers, such that the FIFO is about to overflow and that triggers eTSEC logic to send a PAUSE.
Can the P4040 eSPI controller address 4-byte (32-bit) addressable EEPROMs in any situation? Yes, eSPI controller addresses 4-byte addressable EEPROMs in any situation. For P4040, is it possible to boot from a 4-byte EEPROM using the on-chip ROM? No. The software in the on-chip ROM only supports 16-bit addressable or 24-bit addressable EEPROMs.
Do we have an internal pull up on LA20 pin in P4040E? According to hardware spec for P4040, LA20 pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ pull-down resistor. Assuming that I did not include a pull up or pull down and assuming no device was asserting LA20--what state do we sample at POR? If LA20 is left floating at POR, would one read the SVR for P4040E (80ED0211) OR P1011E (80ED0011)? According to hardware spec for P4040, LA20 pin "must be pulled down with a 4.7K resistor". So the default in case that a design doesn't include an external pull (as required by the spec) is for it to sample as a '1'. Leaving the pin NC (floating) at POR is effectively an out of spec configuration.
For P4040, does DDRCLK and PCIe (SerDes) ref clock support a spread spectrum reference? DDRCLK and PCIe (SerDes) ref clock support spread spectrum. Please note that since SGMII doesn't support spread spectrum, if SGMII is used on any SERDES lane, spread spectrum should not be applied to SERDES REF clock. What are the DDRCLK and PCIe (SerDes) reference clock spread spectrum parameters for P4040? DDRCLK and PCIe (SerDes) reference clock are designed to work with a spread spectrum clock (+0 to –0.5% spreading at 30–33 KHz rate is allowed), assuming both ends have same reference clock. For better results, a source without significant unintended modulation should be used.
The on-chip ROM code does not set up any local access windows (LAWs). Access to the CCSR address space or the L2 cache does not require a LAW. It is the user’s responsibility to set up a LAW through a control word address/data pair for the desired target address and execution starting address (which is typically in either DDR or local bus memory space). Required Configurations for SD Card/MMC Booting The configuration settings required to boot from an SD card/MMC are as follows: Ensure that cfg_rom_loc[0:3] (Boot_Rom_Loc) are driven with a value of 0b0111. Only one core can be in booting mode. If your device has multiple cores, all other cores must be in a boot hold-off mode. The CPU boot configuration input, cfg_cpux_boot, should be 0, where x is from 1 to n (n = the number of cores). Booting from the eSDHC interface can occur from different SD card slots if multiple SD card slots are designed on the board. In this case, ensure the appropriate SD card/MMC is selected For example, on the P4080 board, bit 7 of the SW8 is used to select which SD/MMC slot is used. If SW8 = 1, an SD card/MMC must be put to the external SD card/MMC slot (J1). TIP The polarity of the SDHC_CD signal should be active-low. Required Configurations for EEPROM Booting The configuration settings required to boot from an EEPROM are as follows: Ensure that cfg_rom_loc[0:3] (Boot_Rom_Loc) are driven with a value of 0b0110. Only one core can be in booting mode. If your device has multiple cores, all other cores must be in a boot hold-off mode. The CPU boot configuration input, cfg_cpux_boot, should be 0, where x is from 1 to n (n = the number of cores). The eSPI chip select 0 (SPI_CS) must be connected to the EEPROM that is used for booting. No other chip select can be used for booting. This is because during booting, the eSPI controller is configured to operate in master mode. Booting from the eSPI interface only works with SPI_CS.
Routing the DDR Memory Channel To help ensure the DDR interface is properly optimized, Freescale recommends routing the DDR memory channel in this specific order: 1. Data 2. Address/command/control 3. Clocks Note: The address/command, control, and data groups all have a relationship to the routed clock. Therefore, the effective clock lengths used in the system must satisfy multiple relationships. It is recommended that the designer perform simulation and construct system timing budgets to ensure that these relationships are properly satisfied. Routing DDR3 Data Signals The DDR interface data signals (MDQ[0:63], MDQS[0:8], MDM[0:8], and MECC[0:7]) are source-synchronous signals by which memory and the controller capture the data using the data strobe rather than the clock itself. When transferring data, both edges of the strobe are used to achieve the 2x data rate. An associated data strobe (DQS and DQS) and data mask (DM) comprise each data byte lane. This 11-bit signal lane relationship is crucial for routing (see Table 1). When length-matching, the critical item is the variance of the signal lengths within a given byte lane to its strobe. Length matching across all bytes lanes is also important and must meet the t DQSS parameter as specified by JEDEC. This is also commonly referred to as the write data delay window. Typically, this timing is considerably more relaxed than the timing of the individual byte lanes themselves: Table 1: Byte Lane to Data Strobe and Data Mask Mapping Data Data Strobe Data Mask Lane Number MDQ[0:7] MDQS0, MDQS0 MDM0 Lane 0 MDQ[8:15] MDQS1, !MDQS1 MDM1 Lane 1 MDQ[16:23] MDQS2, !MDQS2 MDM2 Lane 2 MDQ[24:31] MDQS3, !MDQS3 MDM3 Lane 3 MDQ[32:39] MDQS4, !MDQS4 MDM4 Lane 4 MDQ[40:47] MDQS5, !MDQS5 MDM5 Lane 5 MDQ[48:55] MDQS6, !MDQS6 MDM6 Lane 6 MDQ[56:63] MDQS7, !MDQS7 MDM7 Lane 7 MECC[0:7] MDQS8, !MDQS8 MDM8 Lane 8 DDR Signal Group Layout Recommendations Table 2 lists the layout recommendations for DDR signal groups and the benefit of following each recommendation: Table 2: DDR Signal Groups Layout Recommendations Recommendation Benefit Route each data lane adjacent to a solid ground reference for the entire route to provide the lowest inductance for the return currents Provides the optimal signal integrity of the data interface Note: This concern is especially critical in designs that target the top-end interface speed, because the data switches at 2x the applied clock When the byte lanes are routed, route signals within a byte lane on the same critical layer as they traverse the PCB motherboard to the memories Helps minimize the number of vias per trace and provides uniform signal characteristics for each signal within the data group Alternate the byte lanes on different critical layers Facilitates ease of break-out from the controller perspective, and keeps the signals within the byte group together