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As P1025RM.pdf shows, one can multiplex some pins such as, LAD8/GE_PA0 multiplexing. My design uses LOCAL BUS (nor flash) and UTOPIA at the same time. Can I design my product like this in view of pin multiplexing? LAD8 must be used as local bus pin. For UTOPIA, this pin serves as PA0, which is UTOPIA TX address 4. Usually this UTOPIA signal can be not-used. P1025 Reference Manual chapter 12.5.1.2 states that LAD [0:15] can carry both A [0:15] and A [16:31] via ABSWAP setting switching. How can I use it to skip LAD8 to address local bus device? ABSWAP is not used dynamically. It should be set either 0 or 1 but not be switched from time to time. In this case only A [16:31] (from LAD) is available when ABSWAP is used (set to 1). In this case this can only be used if customer requires 16 bit or fewer address lines. In P1025/P1016, for UTOPIA pins UPC1_RxADDR [2:4]/UPC1_TxADDR [2:4], each signal has two pins described in p1025RM. Based on this, can I use any one of the pins LAD08 or MDVAL for UPC1_TxADDR [4]? For LAD08, I'll assign this pin for LOCAL BUS. Yes, you can use any one of the 2 pins for these signals using PMUXCR register. UPC1_TxADDR [4] can be either the one multiplexed with LAD08 or MDVAL. You can assign LAD08 pin for LOCAL BUS. Also remind you that, UPC1_TxADDR 4] is MSB, if only 4-bit UTOPIA address is needed, just use UPC1_TxADDR [0:3] and this LAD08/UPC1_TxADDR[4] pin can be configured as LAD08 by clearing PMUXCR[QE1] bit to 0. In P1025/P1016, I saw that LOE/ LGPL2/ LFRE in the same line, but in P1016EC.pdf, only LGPL2 is present in B14-pin description and I cannot find LOE/LFRE. Can LOE/LFRE (GPCM read enable) signal use B14-pin? LOE/LFRE (GPCM read enable) signal can use B14-pin. For LGPLx pins, we only put the LPGLx in our hardware spec. You can find all other multiplexed function from P1025/P1016 reference manual.
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For P1013/P1022, when I am using a DDR controller with a 64-bit interface with a 32-bit memory sub system, which lanes should I use? When a 64-bit DDR interface is configured in a 32-bit data bus width, lanes [0:3] (MDQ [0:31]) will be used.
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In a previous document, I went through the basic steps of building SDK 1.3.2 for the first time. Now I'm ready to deploy the images onto my target, a P3041DS system. Fortunately my P3041 already has a U-boot and linux install on it. So I can just try and update the SDK from within U-boot. I boot up my trusty terminal - I use putty, and connect to my local COM port at 115200 baudrate. My Ubuntu server already has a tftp server installed, and I link my images over from the SDK build/deploy/images directory over to the /tftpboot directory. The QorIQ_SDK_Infocenter.pdf document within the install has information on the flash bank usage for the current SDK. Make sure you use the document and flash map from the current SDK, as things change. I ended up with a system that didn't boot when I used the older location for the fman uCode (from SDK 1.x) on the SDK 1.3.2 system. Here is a table from the document that shows the flash map for a couple of the QorIQ DS system. It's important to note here that this covers the NOR flash - which is what I'm currently using. You may want to experiment with using NAND or SPI based flash instead - but for my purposes I'm going to re-image NOR flash. The NOR on these development systems is banked, meaning that the most significant address line is tied to a DIP switch. So I can have multiple images in Flash at one time, and switch between them (especially helpful when I mistakenly corrupt one). I'm currently in bank0 (which is the "current bank" in the table above). From this, I see that the addresses I should be interested in are located at: Name Address rcw 0xe8000000 Linux.uImage 0xe8020000 uBoot 0xeff800000 fman uCode 0xeff40000 device tree 0xe8800000 linux rootfs 0xe9300000 To verify that this is correct, I can dump out my RCW: And I can also dump out my current U-boot (which should always start with an ASCII header identifying it): at this point I can start updating the images directly from my TFTP server. I have my tftp server already defined via the U-boot environment serverip, so I just tftp the U-boot image to a randomly picked address in RAM of 0x100000. The transfer went ok, so I can burn it into flash now. I will first erase the flash starting at 0xeff80000. Since U-boot is 0x80000 size, I'll erase from 0xeff80000 for size 0x80000. Apparently my sectors were protected. So I need to unprotect first, then erase again. And by reading the flash, I verify that it has been erased (erased NOR always reads back all 0xF's) So, now I can burn the flash: I use a binary copy. And then verify that the image was written correctly. Then we go through the same technique with the other images. I'll burn the fman ucode as well: Then for the actual images and dtb, you have an option of burning them, but I'll tftp them instead. For this I created a U-boot environment variable called ramboot, and point the image names to the paths on my server: At this point I can save the environment to flash via a saveenv command in U-boot. I'll re-boot into the new U-boot to make sure it works (if it doesn't for some reason, I can jump back to a different U-boot I had previously burned in the alternate bank, or else I'll have to use a debugger to re-burn the flash). Then, from within U-boot I can run ramboot, and if all goes well it should fetch the images and boot all the way into the new SDK. Eventually it should boot all the way to a linux prompt.
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If unused, how do I terminate following pins in P1011/P1020: SDHC_DATA[0:2], SDHC_DAT3, SPI_CS[0:3]/SDHC_DAT[4:7] and SPI_CS0_B/SDHC_DATA4? All the 3 pins SDHC_DATA[0:2], SDHC_DAT3 and SPI_CS[0:3]/SDHC_DAT[4:7] should be don't care if not used. Please leave SPI_CS0_B.SDHC_DATA4 as floating when not used. I have designed my P1011 board based on the older hardware spec, and found that AVDD_CORE0 and AVDD_CORE1 were swapped in newer hardware spec. At this time, it is difficult to cut the pattern for the current AVDD_CORE1. So 1.0V power applied to AVDD_CORE1 though core 1 is not used. Does this cause any problem? If AVDD_CORE1 is powered in single core device, there'll be no problem. But if AVDD_CORE0 is not powered in single core device, the device may not boot up. How should I handle pin W26,F16 pins in P1020? Just let them "NC", or need connect them to AVdd? If AVDD_CORE1 is not powered up i.e. connected to 1.0V, the single core p101x device cannot be boot up. Please implement the AVDD circuit at this stage.
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Time division multiplexing(TDM) is a communication term for multiplexing several channels on the same link. QUICC multi-channel controller(QMC) is a firmware package which uses a unified communication controller(UCC) working in slow mode. The QMC is used to emulates up to 64 time-division serial channels through a time-division-multiplexed(TDM) physical interface. Each of QMC channels can be independently programmed to support either HDLC or transparent protocols. This document introduces TDM QMC driver implementation in Linux Kernel for the processors with QE UCC working in slow mode. Data flow over a QMC channel involves a TDM line and a UCC, working in slow mode. For each channel, Tx data flow consists of data transfer from the external memory to the TDM physical connection. Rx data flow consists of data transfer from the TDM physical connection to the external memory. In both data flows, the major stations are: data buffers, UCC, and the TDM line. Please refer to the following figure for the data flow, the driver requires to configure two levels of routing tables. The first level consists of the SI RAM routing tables, Tx and Rx, which are common to other controllers as well. 1. QE TDM QMC Driver Introduction 2. Driver Architecture and Components 2.1 QMC Driver Memory Allocation 2.2 QMC and TDM Devices Initialization 2.2.1 SI RAM entry initialization 2.2.2 UCC Slow Mode QMC Initialization 2.2.3 QMC Channel Initialization 2.2.4 QMC TSA Slot Initialization 2.3 QMC Channel Interrupt Handling 2.4 QMC and TDM Configuration 2.4.1 Enable and Configure QMC Channel 2.4.2 Enable QMC 2.4.3 Enable TDM 3. QMC TDM Driver Calling Sequence 4. QMC TDM DTS Definition 5. Configure QMC TDM Driver and Running the Testing Program
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For P1021 eTSEC, can I connect eTSEC RGMII with other vendor CPU/FPGA which also supports RGMII Ethernet MAC? In other words, the other side of eTSEC is not a PHY, but a MAC. You can definitely do that but you should remember to connect TX signals of P1021 to RX signals of another MAC and vice versa for MAC mode RGMII as shown below: P10xx_TXD [0:3] -> FPGA_RXD [0:3] P10xx_TX_CTL->FPGA_RX_CTL P10xx_TX_CLK->FPGA_RX_CLK P10xx_RXD [0:3]<-FPGA_TXD[0:3] P10xx_RX_CTL<-FPGA_TX_CTL P10xx_RX_CLK<-FPGA_TX_CLK Also, you have to take the clock delay into consideration. If I didn’t use RGMII, can MDIO/MDC and LVdd be configured at 3.3V for P1012/P1021? The LVdd bank can be operated at 2.5V (for RGMII) and 3.3V(MII/RMII). All the eTSEC IOs including MDIO and MDC can operate at both the voltages. I measured the rise/fall time for RMII interface (800ps) to be lower than P1012/P1021 hardware Spec requirement (min 1ns). Is that a problem? How can I rectify it? When a requirement/condition is specified in hardware spec, it means that we test/guarantee our device to work at that particular condition. For RMII, the hardware spec is inherited from the RMII spec, which states that the rise and fall time should be from 1ns to 5ns. The reason behind is that the RMII spec wants to simplify the layout requirement such that no termination or impedance matching is needed. Although it can be said that a faster rise/fall time is not likely to cause a failure, in order to meet the hardware spec and/or the RMII spec, below steps are recommended: 1. match impedance and add serial termination for the CLK, or 2. use a slower CLK source
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Section 4.4.3.11 in Reference Manual states, "Note that if SGMII mode is not selected on eTSEC1, then it is configured to be in RGMII mode." Yet the MAC is coming up disabled, not RGMII. How can I configure eTSEC1 in RGMII mode in this case? It is not possible to configure eTSEC1 in RGMII mode once it's configured in SGMII mode via POR configs. TSEC1 MAC appears to be disabled when set to mode "11" Table 4-19. Looking at the Table 15-17, it appears if I have them set ECNTRL fields and MACCFG2[I/F] fields for interface mode RGMII, with cfg_io_ports[0:1] = 11, then that should set TSEC1 to RGMII properly, with 2 independant PCIe X1 ports on SerDes SD2. Is that correct? DEVDISR[TSEC1] is 0 at reset. DEVDISR[TSEC2] = n => if PCIe is configured as x4 or SERDES is disabled, DEVDISR[TSEC2] will be disabled. DEVDISR[TSEC3]= n => if TSEC1 is used in MII, TSEC3 can be used only in SGMII. if PCIe is configured as x4 or SERDES is disabled, DEVDISR[TSEC3] = 1. Which P1010 TBI PHY register bit(s) should be used to determine SGMII link status? Is this the Remote Fault and Link Status bits of the P1010 TBI Status Register (SR) which is documented in section 15.5.4.1.2 of the P1010 Reference Manual?  Yes, this is the register (SR) which indicates link status and the above mentioned bits (Link Status/Remote Fault) are used to determine SGMII link status. The meaning of Remote Fault flag is that the PHY is not hearing (code group alignment is lost) the local end (MAC) and is sending this alarm towards the local end in hope the opposite direction works. This flag indicates unstable communication. Try reading it several times since each read clears it. If it reappears, there is something really wrong or misconfigured. The PHY normally shouldn't propagate this flag from the cable side, but check with its' documentation for the case. Read the PHY status through the management interface (MDIO) to check the status of the external link (the MIIMSTAT register). How does the P1010 TBI PHY register access work? Is only the local TBI PHY accessible from a given eTSEC's MDIO register interface or does assigning all TBI PHYs the same address result in collisions? P1010 TBI PHY register are read and written through the eTSEC MDIO registers just like external PHY registers. The address of each TBI PHY is set in the memory mapped TBIPA—TBI PHY address register. The uBoot TSEC device driver assigns the address 0x1f to all three TBI PHYs in the P1010 in their respective TBIPA registers. For the internal TBI block this is controlled by the TBIPA register for each eTSEC block. The reset value of this register is 0x0, which is not a valid PHY address. Therefore this register must be initialized for each TBI (thus SGMII) port in the system. For external PHY devices the address is typically a pin strapping option, so the designer must ensure that the PHY addresses of the external phys are different from any internal TBI that may be sharing that management interface.
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For P1015, does DDRCLK and PCIe (SerDes) ref clock support a spread spectrum reference? DDRCLK and PCIe (SerDes) ref clock support spread spectrum. Please note that since SGMII doesn't support spread spectrum, if SGMII is used on any SERDES lane, spread spectrum should not be applied to SERDES REF clock. What are the DDRCLK and PCIe (SerDes) reference clock spread spectrum parameters for P1015?  DDRCLK and PCIe (SerDes) reference clock are designed to work with a spread spectrum clock (+0 to –0.5% spreading at 30–33 KHz rate is allowed), assuming both ends have same reference clock. For better results, a source without significant unintended modulation should be used.
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Can you give detailed information about P1011/20 clock in sources - SYSCLK, DDCCLK and eTSEC_Clock_125? Do these CLOCK source in support Spread Spectrum? What about SD_REF_CLK/SD_REF_CLK#? The spread spectrum parameters table in P1020 HW Spec is valid for SYSCLK and DDRCLK. Spread spectrum clock is not supported for EC_GTX_CLK125 (RGMII). For SERDES, SD_REF_CLK/SD_REF_CLK_B are designed to work with a spread spectrum clock (+0 to –0.5% spreading at 30–33 KHz rate is allowed), assuming both ends have same reference clock. For better results, a source without significant unintended modulation should be used. Please note that since SGMII doesn't support spread spectrum, if SGMII is used on any SERDES lane, spread spectrum should not be applied to SERDES REF Clock.
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P1010 has only a single pair of MCK signal, while my device has four Chip Select signals. In a scenario connecting a lot of memory devices under four CS, can the single pair of MCK really drive all of memory devices which are connected by fly-by topology on each CS? In case of P1010 (which has only one MCK), is it really practical to connect DDR3 memory devices under all of four CS? Would it be necessary to use "external CLK buffer" in such a case using four CS? P1010 was designed for low-cost systems, and as such some of the pins seen on other QorIQ devices (CKE2/3, ODT2/3) were removed to save on cost. For a single-rank, fly-by topology, only one CS would be used. If more ranks were needed, this would be addressed with stacked memories (DDR3 devices that take up to four CS signals). How does one set up the P1010 or P1014 for a 16 bit data bus size? To set the data bus width, you need to set DDR_SDRAM_CFG[DBW] bits of the register given in section 9.4.1.7, Page-9-20 of P1010RM Rev-B. Is it allowed to use four chip-selects with P1010? In my understanding, one ODT signal should be used and be controlled per chip-select? However P1010 has two MODT. P1010 is designed to use only one chip select with discrete DDR3 DRAM. This requires one CS, one ODT, and one CKE with one clock pair. Additional CS/ODT/CKE are designed for using stacked die DDR3 DRAMs. The four CS, two ODT & CKE, are useful if dual or quad stacked die discrete DDR3 DRAM were used. For the write leveling, does the P1010 use DQ[0,8,16,24] or use all DQ bit to drive status back to the DDR controller? P1010 DDR controller can support the write leveling status on any of the data bits within the data byte from a JEDEC standard DDR3 SDRAM.
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Usually, when I turn on the option of "reset target on launch" CW resets CPU again while connecting to CPU. With P1015, CodeWarrior (CW) does not connect to CPU when the option is on, only when I disable the option, CW can connect to CPU. What could be the problem? . "Reset target on launch" asserts HRESET to the target, thereby resetting the hardware. In most cases this is a required step, but where you don't want to assert HRESET or where your Target Initialization (.cfg) file does this for you with the "reset 1" command, you can do without this option enabled. "P10xx-P20xxRDB_P1011_jtag.txt" JTAG Configuration file is required by 8.8 CW PA for all single-core P10xx processors. Please load the “P20xxRDB_P1011_jtag.txt" JTAG Configuration file in your USB TAP configuration panel you mentioned about. 1) Set MACCFG1[Rx_Flow] && MACCFG1[Tx_Flow] to 1 2) Set RCTRL[LFC] to 1.
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Routing the DDR Memory Channel To help ensure the DDR interface is properly optimized, Freescale recommends routing the DDR memory channel in this specific order: 1. Data 2. Address/command/control 3. Clocks Note: The address/command, control, and data groups all have a relationship to the routed clock. Therefore, the effective clock lengths used in the system must satisfy multiple relationships. It is recommended that the designer perform simulation and construct system timing budgets to ensure that these relationships are properly satisfied. Routing DDR3 Data Signals The DDR interface data signals (MDQ[0:63], MDQS[0:8], MDM[0:8], and MECC[0:7]) are source-synchronous signals by which memory and the controller capture the data using the data strobe rather than the clock itself. When transferring data, both edges of the strobe are used to achieve the 2x data rate. An associated data strobe (DQS and DQS) and data mask (DM) comprise each data byte lane. This 11-bit signal lane relationship is crucial for routing (see Table 1). When length-matching, the critical item is the variance of the signal lengths within a given byte lane to its strobe. Length matching across all bytes lanes is also important and must meet the t DQSS parameter as specified by JEDEC. This is also commonly referred to as the write data delay window. Typically, this timing is considerably more relaxed than the timing of the individual byte lanes themselves: Table 1: Byte Lane to Data Strobe and Data Mask Mapping Data Data Strobe Data Mask Lane Number MDQ[0:7] MDQS0, MDQS0 MDM0 Lane 0 MDQ[8:15] MDQS1, !MDQS1 MDM1 Lane 1 MDQ[16:23] MDQS2, !MDQS2 MDM2 Lane 2 MDQ[24:31] MDQS3, !MDQS3 MDM3 Lane 3 MDQ[32:39] MDQS4, !MDQS4 MDM4 Lane 4 MDQ[40:47] MDQS5, !MDQS5 MDM5 Lane 5 MDQ[48:55] MDQS6, !MDQS6 MDM6 Lane 6 MDQ[56:63] MDQS7, !MDQS7 MDM7 Lane 7 MECC[0:7] MDQS8, !MDQS8 MDM8 Lane 8 DDR Signal Group Layout Recommendations Table 2 lists the layout recommendations for DDR signal groups and the benefit of following each recommendation: Table 2: DDR Signal Groups Layout Recommendations Recommendation Benefit Route each data lane adjacent to a solid ground reference for the entire route to provide the lowest inductance for the return currents Provides the optimal signal integrity of the data interface Note: This concern is especially critical in designs that target the top-end interface speed, because the data switches at 2x the applied clock When the byte lanes are routed, route signals within a byte lane on the same critical layer as they traverse the PCB motherboard to the memories Helps minimize the number of vias per trace and provides uniform signal characteristics for each signal within the data group Alternate the byte lanes on different critical layers Facilitates ease of break-out from the controller perspective, and keeps the signals within the byte group together
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Does P1025 support 16 bits DDR3? I found DDR_SDRAM_CFG{DBW] can be set to 16bits. But no 16bits DDR3 feature is claimed? Theoretically the DDR controller supports 16 bit mode. But the mode has not been tested/verified/validated in P1025. We recommend you to not use 16 mode of P1025. “In asynchronous mode, the memory bus clock speed must be less than or equal to the CCB clock rate which in turn must be less than the DDR PLL rate." Is this statement correct for P1025? No it is not correct. The correct statement is " In asynchronous mode, if the ratio of the DDR data rate to the CCB clock rate is greater than 3 :1 ( i.e. DDR=3:CCB=1 ), than the DDR performance monitor statistic accuracy cannot be guaranteed."
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Routing the DDR Memory Channel To help ensure the DDR interface is properly optimized, Freescale recommends routing the DDR memory channel in this specific order: 1. Data 2. Address/command/control 3. Clocks Note: The address/command, control, and data groups all have a relationship to the routed clock. Therefore, the effective clock lengths used in the system must satisfy multiple relationships. It is recommended that the designer perform simulation and construct system timing budgets to ensure that these relationships are properly satisfied. Routing DDR3 Data Signals The DDR interface data signals (MDQ[0:63], MDQS[0:8], MDM[0:8], and MECC[0:7]) are source-synchronous signals by which memory and the controller capture the data using the data strobe rather than the clock itself. When transferring data, both edges of the strobe are used to achieve the 2x data rate. An associated data strobe (DQS and DQS) and data mask (DM) comprise each data byte lane. This 11-bit signal lane relationship is crucial for routing (see Table 1). When length-matching, the critical item is the variance of the signal lengths within a given byte lane to its strobe. Length matching across all bytes lanes is also important and must meet the t DQSS parameter as specified by JEDEC. This is also commonly referred to as the write data delay window. Typically, this timing is considerably more relaxed than the timing of the individual byte lanes themselves: Table 1: Byte Lane to Data Strobe and Data Mask Mapping Data Data Strobe Data Mask Lane Number MDQ[0:7] MDQS0, MDQS0 MDM0 Lane 0 MDQ[8:15] MDQS1, !MDQS1 MDM1 Lane 1 MDQ[16:23] MDQS2, !MDQS2 MDM2 Lane 2 MDQ[24:31] MDQS3, !MDQS3 MDM3 Lane 3 MDQ[32:39] MDQS4, !MDQS4 MDM4 Lane 4 MDQ[40:47] MDQS5, !MDQS5 MDM5 Lane 5 MDQ[48:55] MDQS6, !MDQS6 MDM6 Lane 6 MDQ[56:63] MDQS7, !MDQS7 MDM7 Lane 7 MECC[0:7] MDQS8, !MDQS8 MDM8 Lane 8 DDR Signal Group Layout Recommendations Table 2 lists the layout recommendations for DDR signal groups and the benefit of following each recommendation: Table 2: DDR Signal Groups Layout Recommendations Recommendation Benefit Route each data lane adjacent to a solid ground reference for the entire route to provide the lowest inductance for the return currents Provides the optimal signal integrity of the data interface Note: This concern is especially critical in designs that target the top-end interface speed, because the data switches at 2x the applied clock When the byte lanes are routed, route signals within a byte lane on the same critical layer as they traverse the PCB motherboard to the memories Helps minimize the number of vias per trace and provides uniform signal characteristics for each signal within the data group Alternate the byte lanes on different critical layers Facilitates ease of break-out from the controller perspective, and keeps the signals within the byte group together
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Please specify the DDR read only and write only counters for P1023. Event 19 counts DDR reads only while event 27 counts DDR writes only in P1023. How are DDR errors cleared in the ESUMR reg (bit 8)? Do they need to re-init the DDR? You need to clear the ERR_DEFECT [MBE] bit (write 1 to clear). After that the ESUMR bit 8 will be cleared.
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Does P1016/P1025 come with SerDes clocks enabled? Will P1016/P1025 remain in reset if the SERDES is enabled and no SerDes reference clock is available? Yes, P1016/P1025 comes with SerDes clocks enabled. However, P1016/P1025 doesn't wait for SERDES PLL lock for it to come out of reset. For P1016/P1025, which jitter spec (tCLK_DJ, tCLK_TJ or tCLK_DJ+tCLK_TJ) should the buffer and oscillator require to meet? The input jitter at the SD_REF CLK input is specified, Buffer vendor will have to provide jitter at the output in pk-to-pk terms so that it can be compared with the Tj at SD_REF CLK input What is the relationship between RMS jitter and peak-to-peak jitter in P1016/P1025? How can I calculate the RMS jitter value from our peak-to-peak jitter value (42 ps and 86 ps)? RMS jitter is only valid for Random (Gaussian distribution) jitter. This rms value is then converted to pk-to-pk value and added to Deterministic jitter (pk-to-pk) for finding the total jitter (in pk-to-pk). For SD_REF CLK, the HW specs state the value for Total jitter (in peak to peak ps) and Deterministic jitter (in peak to peak ps). rms value for Rj can be referred from PCI Express™ Jitter and BER Revision 1.0. Converting the rms to pk-to-pk is not going to help here because the buffer datasheet states the additive phase jitter. This is measured by integrating the phase noise over the frequency band of interest. DDR. “In asynchronous mode, the memory bus clock speed must be less than or equal to the CCB clock rate which in turn must be less than the DDR PLL rate." Is this statement correct for P1025? No it is not correct. The correct statement is " In asynchronous mode, if the ratio of the DDR data rate to the CCB clock rate is greater than 3 :1 ( i.e. DDR=3:CCB=1 ), than the DDR performance monitor statistic accuracy cannot be guaranteed."
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Referring to P1011 IBIS model, there are models of various pin type. Could you please provide brief description on each model name shown below (Extracted from P1010 IBIS file)? 1) DDR related inputs: ddr2_drvr_18, ddr2_drvr_35, ddr2_rcvr_150, ddr2_rcvr_50, ddr2_rcvr_75, ddr2_rcvr_noterm, ddr3_drvr_17, ddr3_drvr_40, ddr3_rcvr_120, ddr3_rcvr_60, ddr3_rcvr_noterm 2) opdalg_out, pouv_out, rx_pzctl, tx_pzctl, ptrmr100_cm 3) v180_in_wb, v330_in_wb, v250_wb, v250_in_wb, v180_wb, v330_wb For DDR related models: Model name shows DDR type and driver impedance. For example, ddr2_drvr_18 should be used for DDR2 and 18 ohm drive strength. For opdalg_out, pouv_out, ptrmr100_cm, rx_pzctl, tx_pzctl - The pins using these models don't have any other choice of model. For v180_in_wb, v330_in_wb, v250_wb, v250_in_wb, v180_wb, v330_wb - These should be chosen for the interfaces with LVCMOS I/Os like eLBC. The numbers in the name depict the voltage level, e.g. v180_in_wb is applicable for 1.8V receiver. For other models - Those are not utilized directly for any pin so user can ignore them.
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When setting the ABSWP bit (in LBCR) in P1020, are the address bytes swapped or just mirrored? Also, can you confirm that the LBCR [ABSWP] affect every device (chip select) being used by the local bus except for the NAND Flash? By setting ABSWP bit (i.e. ABSWP=1), if address=0x12345678. Then LAD [0:15] = 0x7856 and LA[16:31]=0x5678. LBCR [ABSWP] affect every device (chip select) being used by the local bus except for the NAND Flash What is NAND Flash controller speed and size for P1011? AeLBC can work at 83 MHz. At minimum twc, it can be equal to 2 LCLK i.e. half the frequency of LCLK. The maximum page size supported by eLBC is 2K. If I use one mck to drive all 5 ddr3-chips in P1011, can I use the leveling function? Also, which topology do you recommend for this? Yes, writing leveling function should be used to compensate the additional flight time skew delay between different chips introduced by fly-by topology. However, we do not recommend routing the clock in fly-by topology while address, command and control signals routed by other topology. For more detail of JEDEC DDR3 routing topology, please visit [www.JEDEC.org]. Is a 32-bit data interface the only way to control whether or not ABSWP applies (i.e. ABSWP affects 8 and 16-bit data interfaces but does not affect 32-bit data interfaces)? ABSWP also affects 32-bit interface and it is not advisable to set ABSWP for 32 bit interface as only 16 LSB address gets visible on LAD[0:15] and zeroes are output on the LAD[16:31].
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For a single eTSEC, I am wiring two external devices via both its parallel interface and SGMII I/F at same time, and either of interfaces actually used will be determined by POR configuration pins. Is this usage possible? Yes. Please ensure that you all the related POR config pins are properly driven.
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Do you have any additional info on the USB VBUSCLMP pin. The manual says that it is the divided down Vbus. What is the divisor? The P1010 RDB schematic has a diode protecting this pin. What are the critical specifications for the diode? The diode was supposed to be used for in OTG mode. Since the USB phy in P1010 doesn't support OTG, you may choose to ignore it. The VBUS operates at 5V. But VBUSCLMP operates at 3.3V. So you should implement a potential divider to bring down 5V to 3.3V as shown in RDB. In case using on-chip USB PHY, low-speed mode is not supported at all? Or it can be supported if operating in "Host" mode? Low-speed mode (LS) is supported in Host mode but not in device mode. Can you tell me whether USB internal PHY on P1010 supports UTMI+ Level3 or not? UTMI+ Level3 is supported in P1010 Please advise how power supply to USB port should be controlled when using on-chip USB PHY. Without controlling through IFC bus (via CPLD) like P1010RDB schematic, is there other way to control for it? DRVVBUS should be used to control the external VBUS supply. By mistake this signal has been shown as a ULPI signal in P1010 RM because of which P1010RDB designer have not used it for externals VBUS control. About USBVDD1_8(J21,K21), on HWspec Table1 Notes 20 says that "20.This pin should be connected to Vss through 1μF.No need to supply power to this pin. 1.8V output may be observed on this pin during normal working conditions." Is it okay to tie J21 and K21 pins together and connect to Vss via a "single" 1uF capacitor? Or 1uF cap is required for each pin respectively? It should be okay to combine both the pins and connecting to Vss via single 1uF capacitor. If the whole USB (controller and PHY) is not used, user still needs to supply USBVDD3_3 power, Right? What is the reason?  Yes it is required to provide USBVDD3_3 even if USB controller and PHY are not used at all. This is a requirement from design to keep the logic in a sane state. If the whole USB is not used, does user need to follow power sequencing of USBVDD3_3, assuming USBVDD3_3 supply needs to be present? Following the sequence between USBVDD3_3 and other 3.3V supplies is not required. It is must to provide supply to USBVDD3_3 even if the USB PHY is not used. A suggestion, if USB PHY is not used customer can supply this pin with the same regulator which would be used to supply other 3.3V supply pins of SoC. Make sure that the ramp rate constraint is still followed for USBVDD3_3.
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