Please specify the DDR read only and write only counters for P1023.
Event 19 counts DDR reads only while event 27 counts DDR writes only in P1023.
How are DDR errors cleared in the ESUMR reg (bit 8)? Do they need to re-init the DDR?
You need to clear the ERR_DEFECT [MBE] bit (write 1 to clear). After that the ESUMR bit 8 will be cleared.
