tff1003 Phase Noise

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tff1003 Phase Noise

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jmahn
Contributor I

TFF1003HN is being tested for performance.
Phase Noise results below.

Phase Noise

100Hz   : -75dBc/Hz

1kHz    : -82dBc/Hz

10kHz   : -83dBc/Hz

100kHz  : -85dBc/Hz

Reference Freq : Lock on by 10MHz *5

Loop filter is the value in the application.

We ask if Phase Noise is different from the data sheet at 10 kHz and 100 kHz.

If there is an evaluation board for TFF1003HN, we would like to ask if we can rent it or buy it.

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  • RF

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LPP
NXP TechSupport
NXP TechSupport

These values are worse than those specified in the datasheet.

1.
To achieve the target values, the reference clock with low phase noise must be used. The requirements are listed in the TFF1003HN datasheet Table 10. You can find more about this topic in this user guide:

Example design to generate CW ref. signal for TFF1xxxx
https://www.nxp.com/docs/en/user-guide/UM_TFF1xxxx_cleanupPLL_V2.0.pdf

2.
Any noise/ripple on the supply might convert to excessive phase noise/jitter. For this reason it is very important to implement a clean noise and ripple free supply for reference clock circuit and PLL blocks.

3.
OM17004 demo board can be requested through distributors.
https://eu.mouser.com/ProductDetail/NXP-Semiconductors/OM17004-TFF1003?qs=fAHHVMwC%252BbgHalvoHHUXMA...


Have a great day,

Pavel
NXP TIC

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