qadc+edma__ edma bus error

[izzetozcelik]

Hi

I work with MPC5644a. I am trying to implemente the qadc+edma chain.

Basically, QADC is configured such that it generates DMA requests to arm the CFIFO0.

The QADC is trigerred with Single Scan Software enable bit.

The result fifo RFIFO0 generates the DMA request to move the QADC conversions to the on chip SRAM memory.

I also configured the DMA to generate an interrupt once it has moved all the RFIFO results to the SRAM.

All code is placed onto the SRAM.

TCD0 and TCD1 are as given below.

void initTCD0(void) {

  EDMA.TCD[0].SADDR = (vuint32_t) &QADC_CmdQ0;  /* Load address of source data */
  EDMA.TCD[0].SSIZE = 2;                        /* Read 2**0 = 1 byte per transfer */
  EDMA.TCD[0].SOFF = 4;                         /* After transfer, add 1 to src addr*/
  EDMA.TCD[0].SLAST = numOfcommands * -4;                      /* After major loop, reset src addr*/
  EDMA.TCD[0].SMOD = 0;                         /* Source modulo feature not used */

  EDMA.TCD[0].DADDR = CFIFO0_PUSH;     /* Load address of destination */
  EDMA.TCD[0].DSIZE = 2;                        /* Write 2**0 = 1 byte per transfer */
  EDMA.TCD[0].DOFF = 0;                         /* Do not increment destination addr */
  EDMA.TCD[0].DLAST_SGA = 0;                    /* After major loop, no dest addr change*/
  EDMA.TCD[0].DMOD = 0;                         /* Destination modulo feature not used */
 
  EDMA.TCD[0].NBYTES = 4;                       /* Transfer 1 byte per minor loop */
  EDMA.TCD[0].BITER = numOfcommands;            /* 12 minor loop iterations */
  EDMA.TCD[0].CITER = numOfcommands;            /* Initialize current iteraction count */
  EDMA.TCD[0].D_REQ = 0;                        /* Disable channel when major loop is done*/
  EDMA.TCD[0].INT_HALF = 0;                     /* Interrupts are not used */
  EDMA.TCD[0].INT_MAJ = 0;
  EDMA.TCD[0].CITERE_LINK = 0;                  /* Linking is not used */          
  EDMA.TCD[0].BITERE_LINK = 0;
  EDMA.TCD[0].MAJORE_LINK = 0;                  /* Dynamic program is not used */
  EDMA.TCD[0].E_SG = 0;
  EDMA.TCD[0].BWC = 0;                          /* Default bandwidth control- no stalls */
  EDMA.TCD[0].START = 0;                        /* Initialize status flags */
  EDMA.TCD[0].DONE = 0;
  EDMA.TCD[0].ACTIVE = 0;
}

void initTCD1(void) {

  EDMA.TCD[1].SADDR = RFIFO0_POP;        /* Load address of source data */
  EDMA.TCD[1].SSIZE = 1;                       /* Read 2**0 = 1 byte per transfer */
  EDMA.TCD[1].SOFF  = 0;                       /* After transfer, add 1 to src addr*/
  EDMA.TCD[1].SLAST = 0;                       /* After major loop, reset src addr*/
  EDMA.TCD[1].SMOD  = 0;                       /* Source modulo feature not used */

  EDMA.TCD[1].DADDR = (vuint32_t) &QADC_RsltQ0; /* Load address of destination */
  EDMA.TCD[1].DSIZE = 1;                        /* Write 2**0 = 1 byte per transfer */
  EDMA.TCD[1].DOFF  = 2;                           /* Do not increment destination addr */
  EDMA.TCD[1].DLAST_SGA = numOfcommands * -2;      /* After major loop, no dest addr change*/
  EDMA.TCD[1].DMOD = 0;                            /* Destination modulo feature not used */
 
  EDMA.TCD[1].NBYTES = 2;                       /* Transfer 1 byte per minor loop */
  EDMA.TCD[1].BITER = numOfcommands;                       /* 12 minor loop iterations */
  EDMA.TCD[1].CITER = numOfcommands;                       /* Initialize current iteraction count */
  EDMA.TCD[1].D_REQ = 0;                        /* Disable channel when major loop is done*/
  EDMA.TCD[1].INT_HALF = 0;                     /* Interrupts are not used */
  EDMA.TCD[1].INT_MAJ = 1;
  EDMA.TCD[1].CITERE_LINK = 0;                  /* Linking is not used */          
  EDMA.TCD[1].BITERE_LINK = 0;
  EDMA.TCD[1].MAJORE_LINK = 0;                  /* Dynamic program is not used */
  EDMA.TCD[1].E_SG = 0;
  EDMA.TCD[1].BWC = 0;                          /* Default bandwidth control- no stalls */
  EDMA.TCD[1].START = 0;                        /* Initialize status flags */
  EDMA.TCD[1].DONE = 0;
  EDMA.TCD[1].ACTIVE = 0;
}

When I run the code, DMA does not generate interrupt since it is kind of stuck due to  destination bus error.

Channel 1 (RFIFO0 --> SRAM) gives a bus error for the destination.

Does anyone have an idea on this. Is it due to XBAR settings?

Best regards

izzet

[davidtosenovjan]

In the header file there is decision block

        /* Select one of the following declarations depending on the DMA mode chosen */

        /* struct EDMA_TCD_STD_tag TCD[64];  */       /* Standard Format   */

        /* struct EDMA_TCD_alt1_tag TCD[64]; */       /* CITER/BITER Link  */

        struct EDMA_TCD_alt2_tag TCD[64];        /* Minor Loop Offset */

        };

By default EDMA_TCD_alt2_tag TCD[64] is chosen. In this version of TCD NBYTES is defined as :

        vuint16_t NBYTES:10; /* inner (“minor”) byte count */

thus as 16-bit value.

So if you perform

        EDMA.TCD[1].NBYTES = 4;

you are touching only lower 16-bit of NBYTES field. Higher 16-bit stay untouched with its default value (random value).

Note that the whole descriptor (every bit) must be initialized because it is basically RAM memory, it does not have any reset value.

[Wlodek_D_]

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