nxp pca2129t oscillator stops when switching form power supply to battery

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nxp pca2129t oscillator stops when switching form power supply to battery

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thomaserb
Contributor I

Hello,

I have a clock device PCA2129T in use. In general the divice works fine. It is powered with 3.3V on Vdd and additionally connected to a battery voltage of 3.1V at Vbat.

Not always but in many cases after switch-off of the power supply at Vdd the oscillator stops. When I measure the battery voltage at Vbat it is constantly about 3V, so the clock should work. But the BBS pin shows a power breakdown to 0V and after a restart with normal power supply the readout of the OSF bit is set and the time within the device is lost.

Sometimes the device neither does stop oscillation nor BBS breaks down nor OSFbit is iset.

What could be reason(s) for this behaviour of the PCA2129T?

Thanks and regards

Thomas

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reyes
NXP TechSupport
NXP TechSupport

Hi Thomas,

 

Several users have application-related concerns when they power-down VDD. VDD ramp down too fast seems to be the most possible cause of the behavior you are seen.

VDD is sampled. If it collapses in between samples then the event is missed and the device fails to switch to battery.

Please ensure that you keep the slew rate at 0.7V/ms or less. If the slew rate is faster than 0.7V/ms, then you can slow it down by adding some decoupling capacitors on the VDD pin.

The functionality of the battery switch-over is limited by the fact that the power supply VDD is monitored every 1 ms in order to save power consumption. Considering that the battery switch-over threshold value (Vth(sw)bat) is typically 2.5 V, the power management operating limit (VDD(min)) is 1.8 V and that VDD is monitored every 1 ms, the battery switch-over works properly in all cases where VDD falls with a rate lower than 0.7 V/ms.

 

I recommend you to check the Application Note AN1186 where you can find more details information about this topic, especially on section 5.3 “Battery switch-over applications”: https://www.nxp.com/docs/en/application-note/AN11186.pdf

 

Regards,

Jose

NXP Semiconductors

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583 Views
reyes
NXP TechSupport
NXP TechSupport

Hi Thomas,

 

Several users have application-related concerns when they power-down VDD. VDD ramp down too fast seems to be the most possible cause of the behavior you are seen.

VDD is sampled. If it collapses in between samples then the event is missed and the device fails to switch to battery.

Please ensure that you keep the slew rate at 0.7V/ms or less. If the slew rate is faster than 0.7V/ms, then you can slow it down by adding some decoupling capacitors on the VDD pin.

The functionality of the battery switch-over is limited by the fact that the power supply VDD is monitored every 1 ms in order to save power consumption. Considering that the battery switch-over threshold value (Vth(sw)bat) is typically 2.5 V, the power management operating limit (VDD(min)) is 1.8 V and that VDD is monitored every 1 ms, the battery switch-over works properly in all cases where VDD falls with a rate lower than 0.7 V/ms.

 

I recommend you to check the Application Note AN1186 where you can find more details information about this topic, especially on section 5.3 “Battery switch-over applications”: https://www.nxp.com/docs/en/application-note/AN11186.pdf

 

Regards,

Jose

NXP Semiconductors

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