Please note that I don't configure DDR and I also have no CPLD in my design,
so basically I only need NOR.
Here is my config file:
writereg MBAR 0xff400000
# change internal MMR base from 0xff400000 (reset value) to 0x80000000
writemem.l 0xff400000 0x80000000 # IMMRBAR = 0x80000000
writereg MBAR 0x80000000
# Relocate 128K SRAM Base Address to 0x00000000
writemem.l 0x800000c4 0x00000000 # SRAMBAR
# LocalPlus Bus Local Access Windows
#####################################
# WINDOW 1 - LocalPlus Boot: 64MB NOR FLASH
writemem.l 0x80000020 0xfc00ffff #LPBAW1 - begining at 0xfc000000
#Configure and Enable Clocks
############################
writemem.l 0x80000f0c 0x01A05330 # 0x01605330 # SCFR1 - IPS_DIV=1/2. PCI_DIV=1/6, MBS_GPX_DIV=1/1. LPC_DIV=1/2, NFC_DIV=1/3
writemem.l 0x80000f04 0xCFFFBC00 # 0xfffffc00 # SCCR1 - enable all clocks
writemem.l 0x80000f08 0xE4000000 # 0xfff80000 # SCCR2 - enable all clocks
##############################################
# Local Plus Controller (LPC) Configuration
##############################################
# CS0 - NOR FLASH
writemem.l 0x80010000 0x05051090 # 0x05051090 waitstates, 8-bit databus, CE, enable write access, non muxed
#LPC_CSCR
writemem.l 0x80010020 0x01000000
writereg MSR 0x3000 # FP available, machine check, exception vectors at 0x0000_0000
# SPCR[TBEN] enable timebase
writemem.l 0x80000104 0x00400000
#unprotect flash
# writemem.b 0x82000008 0xC9 # CPLD Address
#invalidate SP
writereg SP 0xF
Message Edited by grass on 2009-07-12 07:52 AM