e500v2 core: Can't get watchdog to generate machine check.

[muchado]

I'm having trouble getting my MPC8544 watchdog to generate a machine check interrupt on the second interrupt.

According to AN2804 - Watchdog Timer for e500, I set TCR[WRC] = 01 which should cause a processor machine check exception.  I've also verified (using an ICE) that HID0[EMCP]=1 and MSR[ME]=1.  However, when the second watchdog interrupt occurs, the processor freezes up in what I assume is a checkstop.

I've also verified that my watchdog timer is set up correctly by changing only TCR[WRC] = 10 which indeed causes a hard reset when the timer expires.

I've also verified that my machine check interrupt handler code is functioning correctly through generating other machine checks.

Has anyone else gotten the machine check to work?  Am I missing some errata or updated documentation.

Thanks for any insights.

[jabbathespud]

According to the 8544RM,

TCR[WRC]: 01 Force processor checkstop on second timeout of watchdog timer

I see no reason to expect a machine check exception to occur.  If you want an exception, that's what the watchdog timer exception is for.