custom board with sja1105 - configuration

[dadoom]

Greetings!

We have custom board with sja1105PEL on it.

After everything was done as described in manual we have problem at configuration stage.

We need to clarify some points:

sja1105 SPI interface connected to FPGA IO ports.

Dose sja1105 have power on or reset sequence befor or in time of cofiguration process?

At this moment we have that sequence :

   1. power on and RST_N with TRST_N pulled UP so device is active and out of reset from the first moment.

   2. after some time configuration start.

Problem is that we cant read from device. We try to read device ID or status register before or after first block loded and no success.

Read sequence:

    1. ss_n down

    2. half of clk before first rising edge on sclk

    3. 64 ticks of sclk at 10MHz.

    4. at first 32 ticks address loaded in SDI port as 0x02000000 (read one long-word from address 0x0) or 0x02000010 (read one word from address 0x1)

    next 32 ticks on SDI should be ignored and we should take answer from SDO port but...

    5. SDI still mirrored to SDO as at time of writing operation.

    6. half clk from last falling edge.

    7. ss_n up.

Could it be device defect?

In manual stated that MSB go first but dose not mentioned about byte order. We use most significant byte first by default.

During configuration we read status register after every block loaded. Next block write should start from next address. Dose address of avery data long-word incremnt by one? Or by 4 as byte memory write? For example:

    load first block with device ID to address 0x20000. It has 10 long data words so after ID + header + crc + data + crc we have 15 long words loaded. Then read status register. Then next block should be written to 0x2000F or 0x2003C?

Dose sja1105 have some test sequence to check for device defects?

Thank you!

[bpe]

Please find my comments to your questions inline below:

>Dose sja1105 have power on or reset sequence befor or in time of cofiguration process?
[Platon] Yes. See SJA1105PQRS Application Hints (AH1704) Section 2.4. The document

is available on Docstore.

>Read sequence:
>    1. ss_n down
>    2. half of clk before first rising edge on sclk
>    3. 64 ticks of sclk at 10MHz.
>    4. at first 32 ticks address loaded in SDI port as 0x02000000
>    (read one long-word from address 0x0) or 0x02000010 (read one word
>    from address 0x1)

[Platon] This looks generally correct.

> next 32 ticks on SDI should be ignored and we should take answer from SDO port but...
>5. SDI still mirrored to SDO as at time of writing operation.
>    6. half clk from last falling edge.
>    7. ss_n up.

>Could it be device defect?
>
[Platon] In theory, yes. However, I would recommend starting with
SPI timing and frame structure verification. The former is specified
in the switch long datasheet, Section 10 and Tables 15 and 16, the
latter is in the Software Manual, Section 3.

>In manual stated that MSB go first but dose not mentioned about
>byte order. We use most significant byte first by default.
>
[Platon] The switch accepts complete 32-bit words, without breaking them into
bytes. If your SPI master breaks words into bytes, then data shall
be arranged in it's transfer buffers in a way that the switch sees
the frame structure exactly as shown on Figures 3 through 6 of the switch
Software Manual. Consult at your SPI master documentation for it's
transfer buffers layout.

>Dose address of avery data long-word incremnt by one? Or by 4 as
>byte memory write?

[Platon] The device is 32-bit word addressable.

>Dose sja1105 have some test sequence to check for device defects?
>
[Platon] No.

Hope this helps,
Platon

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[dadoom]

Thank you for your answer.

We took time to check everything.

We followed your recomendtions and cheked everything again and again. Formaly everything looks correct but still no success.

We dont have NDA at this moment. So if it possible could you briffly explain what incorrect in our power up sequence?

We know from manual that clock should be stable before switch activation. So we made reqired pause before configuration. What else we should know?

In our designe both JTAG reset and switch reset tied up to one control pin. Could it be the reason?

How should SPI respond to input if device in reset stage (RST_N is active - "low")?

We have two boards with that switch and we checked the second one. Second board do the same thing. Could it be the defected batch of devices? Or what it could be?

[bpe]

First of all, AH1704 is actually a supplement to the chip Datasheet.
It offers important design suggestions and is a must-have for a designer.
Open a Support Case for NDA process, then visit NXP docstore
(https://www.docstore.nxp.com/), register and request access to the
full switch documentation.

As of your powerup and reset sequence, it is different from the recommended
one and can be the problem. You can try this as a quick solution: (a) disconnect
TRST_N from RST_N and leave it unconnected or pull it up via a 10K Ohm resistor
to VDDIO_HOST; (b) Pull RST_N up to VDDIO_HOST via a 10K Ohm resistor and
implement a circuit that drives it actively low for at least 5 uSec after all
power supplies reach their nominal values and  reference clock signals
become stable.

Have a great day,
Platon

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Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
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