When using the FCM to boot an MPC8315 out of large-page nand flash, how many page address cycles are used?
We would like to boot out of a 4Gb large page NAND, which uses two cycles of column address followed by three cycles of page address. The part is a Micron MT29F4G08ABADAWP.
We know that for 1Gb or smaller devices only two cycles of page address are required. We are hoping that the FCM does not assume a 1Gb or smaller flash, that would mean the maximum size NAND we could boot out of would be 128Mbytes, which isn't any larger than we can get using a small page flash part.
I know that we can set the page address cycles after boot using FMR[AL], which in our case we will want FMR[AL]=01 to give us three cycles (bytes). I am just wondering what it uses at power up.
Has anyone out there successfully booted out of a 2Gb or larger NAND flash part?
Solved! Go to Solution.
Can you please explain how you made MPC8315 working with Large NAND. We have recently updated our board (based on MPC 8315) NAND flash from 64 MB to 256 MB Micron MT29F2G08ABAEAH4. But we could not bring up the board.
When i checked with freescale support, i got reply today that 8315 does not support 4-bit ECC as required by Micron.
Your valuable input is more appreciated