Why the address of MIDRn in dts for s32r45 no offset

[aiweixin]

Hi,

    I find the address of SIUL2_0 MIDR1 in S32R45 rm file have 4bytes offerset.

    But, in arch/arm64/boot/dts/freescale/s32r45.dtsi, the address of SIUL2_0 MIDR1 no offset.

    In my opinion, why not as follow?

<MIDR_SIUL2_0 0 0x0 0x4009c004 0x0 0x08>

    Is it related to address alignment? I'm not sure.

[petervlna]

Hello,

Since there are 2 MIDR registers, there must be an offset.

I do not know about the s32r45.dtsi but physically there is offset.

Simply check MIDR registers in debugger.

Best regards,

Peter