Understanding UPM burst mode

[wrostek]

Hi PPC specialists

I'm on the way trying to understand the LBC UPM machine
of my MPC8536. After some time reading and testing I'm
still struggling with my first tests.

What I'm trying to achieve is reading as fast as possible
data blocks from the local bus to e.g. SATA disk. The burst
mode of the UPM seems to be suitable as it avoids an address/
data multiplexing for each read.

For initial tests I hooked into u-boot code to see what's
going on. To verify my program I use an oscilloscope and
look at LCLK, LALE and LCS1.

Here the extracted code setting up the LBC

...
const uint sdram_table[] =
{
        /*  single read. (offset 0 in upm RAM) */
        0x1F07D004, 0xEEAEE004, 0x11ADD004, 0xEFBBA000,    // generates 3 LCS1
        //0x1F07D004, 0xEEAEE004, 0xE1ADD004, 0xEFBBA000,  // generates 5 LCS1
        0x1FF75447, 0x1FF77C34, 0xEFEABC34, 0x1FB57C35,    // generates 3 LCS1
        //0xEFF75447, 0xEFF77C34, 0xEFEABC34, 0x1FB57C35,  // generates 5 LCS1

        /* burst read. (Offset 8 in upm RAM)   */
        0x1F07D004, 0xEEAEE004, 0x00ADC004, 0x00AFC000,
        0x00AFC000, 0x01AFC000, 0x0FBB8000, 0x1FF75447,
        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,

        /* single write. (Offset 0x18 in upm RAM) */
        0x1F27D004, 0xEEAEA000, 0x01B90004, 0x1FF75447,
        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,

        /*  burst write. (Offset 0x20 in upm RAM) */
        0x1F07D004, 0xEEAEA000, 0x00AD4000, 0x00AFC000,
        0x00AFC000, 0x01BB8004, 0x1FF75447, 0xFFFFFFFF,
        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,

        /* Refresh cycle, offset 0x30 */
        0x1FF5DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
        0xFFFFFC84, 0xFFFFFC07, 0xFFFFFFFF, 0xFFFFFFFF,
        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,

        /* Exception, 0ffset 0x3C */
        0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
};
static void _init_upm(void)
{
        volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
        uint lcrr = 0x80000002;

        /* set to 133 MHz (max. for this board) */
        out_be32 (&lbc->lcrr, lcrr);
        asm ("sync;isync;msync");

        out_be32 (&lbc->br1, 0xe00018a1);  /* address 0xe000_0000, 32bit, UPMB, enabled */
        out_be32 (&lbc->or1, 0xffff0000);
        asm ("sync;isync;msync");

        out_be32 (&lbc->ltesr, 0xffffffff);     /* Clear LBC error interrupts */
        out_be32 (&lbc->lteir, 0xffffffff);     /* Enable LBC error interrupts */

        out_be32 (&lbc->mbmr, 0x0);
        upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
}
...

Using the u-boot command for reading from memory
=> md.l e0000000 10
I see a single LALE and 3 LCS1 signals. The command is asking
for and displaying 0x10 data words. Seems not to be ok.

Changing the single read RAM pattern (see the two commented out lines above)
I now see 5 LCS1 signals instead of 3. Means this pattern is found at least.


To force the burst read I give the SATA driver access to this memory.
In my understanding its DMA should ask for one 512 byte block and
find the burst mode.

The first command reads from standard memory and works fine.
The second command reads from UPM address range and responds after a long timeout
with that error.

=> sata write 1000000 70baf7d 1
SATA write: device 0 block # 118206333, count 1 ... 1 blocks written: OK
=> sata write e0000000 70baf7d 1
SATA write: device 0 block # 118206333, count 1 ... Non-NCQ command time out
Wait no active time out
Non-NCQ command time out
1 blocks written: OK
=>

I appreciate any advice how to setup a working example.

Thanks in advance
Wolfgang R.

[genuap]

Is the chip select marked as cacheable? For this sort of processor, burst requests are only made to the memory controller by cacheable core accesses. And the burst size would then typically be a cache line.

 ... Paul

[wrostek]

It seems that my basic assumption is wrong.

The 8536 ref manual is talking about an 'internal
master ... requests burst reads'. I thought that
the DMA controller is such an internal master
capable to make a burst read from local bus to
system memory. But this seems wrong, yes?

The only reason for me looking at the UPM and
not taking the GPCM was to avoid address/data
multiplexing. I thought I can double the speed
via burst reads. E.g. on a 133 MHz local bus
the GPCM will be restricted to 66 MHz data
transfer rate but I thought I can come close
to 133 MHz reading large data segments via UPM
burst from the local bus.

Wolfgang R.

[wrostek]

Thanks Paul for your feedback.

I'm on holdays but will take a look at it next week.

regards

Wolfgang R.