TJA1101B PHY Integration to i.MX8MP

Amal_Antony3331 · ‎11-06-2022

Hi Team,

We are trying to integrate the NXPs TJA1101 Ethernet PHY with i.MX8MP as a 2-wire interface.
One thing to clarify is that, how can we read/write the MDIO PHY registers?
Are there any utilities available for this ?

Any help is appreciated.

Regards

Amal

jimmychan · ‎11-08-2022

FYI.

This is the driver.

nxp-tja11xx.c - drivers/net/phy/nxp-tja11xx.c - Linux source code (v6.0.7) - Bootlin

Amal_Antony3331 · ‎11-09-2022

Hi@jimmychan

I'm able to probe the driver and also set a static IP.

But when I tried to ping to another board which is of same domain, it doesn't work.

So want to read the different status and control register values. So how can we read/write these PHY registers?

jimmychan · ‎11-09-2022

You could add the code in the driver to read/write the PHY.

Amal_Antony3331 · ‎11-14-2022

Hi @jimmychan

I have cross-compiled the attached application for read the PHY registers.
Register values seems to Okay. but still the communication between tx and rx is not happening.

Link is not getting up. (LINK_STATUS register returns zero).

Whether it is the issue with dts configuration?

jimmychan · ‎11-16-2022

What is the configuration of the PHY in your dts file?

Amal_Antony3331 · ‎11-16-2022

hi @jimmychan

&fec {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_fec>;
        phy-mode = "rmii";
        phy-handle = <&ethphy1>;
        fsl,magic-packet;
        status = "okay";

        mdio {
                compatible = "fsl,nxp-tja11xx";
                #address-cells = <1>;
                #size-cells = <0>;

                ethphy1: ethernet-phy@0 {
                         compatible = "ethernet-phy-ieee802.3-c22";
                        reg = <0>;
                        eee-broken-1000t;
                        rtl821x,aldps-disable;
                        rtl821x,clkout-disable;
                };
        };
};

        pinctrl_fec: fecgrp {
                fsl,pins = <
                        MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC               0x3
                        MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO              0x3
                        MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0         0x91
                        MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1         0x91
                        MX8MP_IOMUXC_SAI1_TXD7__ENET1_TX_ER             0x1f
                        MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL      0x1f
                        MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0         0x1f
                        MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1         0x1f
                        MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL      0x91
                        MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER             0x1f
                        MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK            0x3
/*                      MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2         0x91 */
/*                      MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3         0x91 */
/*                      MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC          0x91 */
/*                      MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2         0x1f */
/*                      MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3         0x1f */
/*                      MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC         0x1f */
/*                      MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02              0x19 */
                >;
        };