TJA1043 ERR_N pin query

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TJA1043 ERR_N pin query

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Rashmi073
Contributor I

Hi NXP team,

We have below queries on TJA1043 ERR_R pin ..can you please clarify?

1. ERR_N pin state is getting change during Bus off (CANH to GND/CANL to VBAT)

When CANH to GND, ERR_N pin is toggling

When CANL to VBAT, ERR_N pin is low

Because of the ERR_N pin state got changed during Bus off, we are setting the fault for both Bus off and ERR_N monitoring. can you please please confirm whether this is the expected behavior?

2. When we make CANH to VBAT or CANL to GND, CAN communication should be happen or not?

Because some times CAN communication is happening and sometimes is not happening.

3. What is the minimum load should be connected at the terminals(between CANL to CANL) to simulate the local bus failure?

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3 Replies

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ErikaC
NXP TechSupport
NXP TechSupport

Hello

1. The ERRN pin will indicate different faults depending on the state of the mode control pins, it cannot be guaranteed, that the ERRN pin is statically LOW and as such permanently indicating the bus fault condition. This is caused by all kind of topology related and e.g. CAN common mode choke related effects on the wiring harness. Nevertheless, the ERRN does not transition LOW, if there is no bus fault condition. So, any active LOW signal on ERRN is a strong indicator for a true bus short condition.

2. In this state communication may still be possible but bit timing errors may occur, this would depend somewhat on the network setup.

If the device is still able to generate the required differential voltage, it will be detected by the other node.

Regards.

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ErikaC
NXP TechSupport
NXP TechSupport

Hello,

Question 1, could you clarify the question? I think the chapter I mention below clarifies this question, but I am not sure if it is about flag stability.

Question 2, for more information, please refer AH1014, Chapter 6.6 and 10.1.4 (pin FMEA).

ErikaC_0-1669734686876.png

Question 3, we recommend a load of about 60 Ohms.

Hope it helps. 

Regards.

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362 Views
Rashmi073
Contributor I

Question 1: do you mean that ERR_R pin state can change if any of CANH or CANL lines are connected to VBAT /GND?


Question 2.What if the communication is not happening when CANH to VBAT /CANL to GND short?


would it possible to have a call to discuss about this topic as it is bit prio?

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