SJA1110 VDDIO MIIx

[enrov]

I have an issue using VR5510 in companion with SJA1110. Short story long: if the SJA1110 is keep in HARD RESET and I power up the VR5510 from external source, the LDO2 connected to VDDIO 1.8V MII power supply rail startup in instability generating 2.2V instead of 1.8V (i think that voltage can rise up to Vin 3.3V if not limited by some SJA1110 internal clamp)

Attached the portion of the schematic from NXP  SJA1110-EVM board that is exactly what I used on my custom board.

I'm monitoring the 1.8V voltage with VR5510 internal voltage monitors, in that case VR5510 PGOOD never change state because of OVERVOLTAGE detected.

Very strange thing is that if I disconnect PGOOD pin from SJA1110 HARD RESET pin, i have no issues and PMIC start successfully together with SJA1110.

I was looking about the reset state of the power supply rails, but they are not defined. Is it possible that during HARD RESET, the VDDIO of the MIIx interfaces are tied up to other VDDIO at different voltage, for example 3.3V? 

Should i keep reset on HARD RESET and CORE RESET together? Actually they are separated and CORE RESET is tied up to 3.3V and not managed.

Thank you

enrov

[enrov]

For community: no issues with SJA, following the AH725720 as suggested. Quick dirty workaround to be verified by user is to add a pulldown (weak) to VDDIO_MIIx line to avoid uncontrolled voltage rise. 

[enrov]

Yes thank you, I'm going to replay to you soon.

Just a correction to my previous post: my design is really similar to SPF-47966.pdf not to KITVR5510SKTEVM. Sorry for that.

Regards

[PavelL]

Hello @enrov ,

I can see that on SJA1110-EVM, PGOOD of VR5510 is not connected to the HARD_RESET_N - the resistor R363 is not populated.

MIIx interfaces are always connected to their dedicated supplies.

Please refer to SJA1110 Hardware Application Note [AH725720] available in the Documentation section, under Secure files, for details about handling RST_N and RST_CORE_N.

Best regards,

Pavel

[enrov]

Hello Pavel

thank you for your reply

On the board I'm testing the two RSTs are tied together. Due to the RST loop that i have (PMIC is resetting the SJA because 1.8V is OV), I'm using an second external voltage monitor only on 3.3V which, after 200ms, It releases the RSTs letting startup the board without other any issues.

From oscilloscope, i can see that:

- immediatly after power up PMIC, 1.8V output voltage is preset on VDDIO_MIIx 

- with an expoential RC charge, the voltage rises in 100ms to 2.2V without any apparent reason

- as soon after 200ms (and the external voltage monitor release RSTs) the VDDIO_MIIx pass from 2.2V to 1.8 letting start the board without any other issues.

On RMII ports I have two Atheros, for your information the board is very similar to KITVR5510SKTEVM.

I have no Atheros RST management, but doing an experiment with an external wire on Atheros RSTs tied together with SJA RSTs, behavior does not change.

So my question is: considering that I manage the RST as suggested in AH725720, Is it plausible that an uncontrolled voltage flow inside the SJA during reset and it is reflected to VDD rails?

What other precaution should I have taken?

Regards

[PavelL · Accepted solution]

Hello @enrov ,

I need more data from your side. I sent you an email.

Best regards,

Pavel