Kevin (@kaden),
Goal is to have the switch programmed to be a "dumb" L2 switch, fully-meshed, all ports able to route traffic to all ports w/o restrictions. I generated a configuration using the software package above. The key difference being a change to line 94 of simplePQRS.py
"HOST_PORT" : 99, # no host port
As for this configuration, all ports will be used to move traffic. Programmed the resulting file on the target, checked that bit 31 of register 1 is set.
My board is wired for RGMII, this matches with what I see at the mii_mode_parameters set in line 364. I can see I have link-up but for my connected phys, but I'm not seeing traffic going between ports on the switch.
Reading the simplePQRS.py file, it seems to do what I'm looking for it do to (fully meshed, no tagging, on traffic shaping, etc), can you let me know if that's a correct read of the configuration file?
(edit) I was going through the datasheet, and looking at table 72, I found the N_SOFERR counter ticking upwards for the two ports I had connected. Will read through sheet to see if this is the result of some settings or if I need to get help from my EE team.
Thanks for your help,
gene