SGTL5000 with 1.8V VDDIO and 3.3V VDDA

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SGTL5000 with 1.8V VDDIO and 3.3V VDDA

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Contributor II

Dear All,

We have a custom board configured with 1.8V VDDIO, 1.8V  VDDD and 3.3V VDDA. We can read and write to the chip via I2C. The I2S bus has all of the necessary signals, including MCLK, but we are unable to see any analog output on Line Out.

We are wondering if there is any aspect of the chip power supply configuration peculiar to 1.8V VDDIO and 3.3V VDDA operation that would impact this.

We are running with a 4.9 series Linux kernel on an NVIDIA TX2i module with the driver supplied with Jetpack 4.4.

Any hints appreciated.

David

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Contributor II

Hi,

I believe we have figured out what was going on. When we examined the power supply configuration code in the Linux driver, we saw the following (voltages here are given in mV):

 

if (vddio < 3100 && vdda < 3100) {
		/* enable internal oscillator used for charge pump */
		snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
					SGTL5000_INT_OSC_EN,
					SGTL5000_INT_OSC_EN);
		/* Enable VDDC charge pump */
		ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
	} else {
		ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP;
		/*
		 * if vddio == vdda the source of charge pump should be
		 * assigned manually to VDDIO
		 */
		if (regulator_is_equal(sgtl5000->supplies[VDDA].consumer,
				       sgtl5000->supplies[VDDIO].consumer)) {
			lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
			lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
				    SGTL5000_VDDC_MAN_ASSN_SHIFT;
		}
	}

 

As our intended VDDA supply was 3.3V, we did not require charge pump operation, so this branch was never invoked. The only other option supported, involving either VDDIO or VDDA exeeding 3.1V, then made a manual assignment of VDDC to the VDDIO supply. However, with our selection of VDDIO = 1.8V, this configuration would not allow the internal analogue switches in the SGTL5000 to operate. In other words, the stock Linux driver did not support VDDIO = 1.8V making it impossible for the device to produce audio output, despite appearing to operate correctly in every other sense.

On review of the SGTL5000 data sheet, it was apparent that an automatic voltage selection mode was actually supported, and the modified driver code snippet below was shown to reliably select VDDA as the source for VDDC in our configuration. This was confirmed by measuring 3.3V on pin 18 (CPFILT) of the chip.

 

if (vddio < 3100 && vdda < 3100) {

		/* enable internal oscillator used for charge pump */
		snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
					SGTL5000_INT_OSC_EN,
					SGTL5000_INT_OSC_EN);
		/* Enable VDDC charge pump */
		ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
	} else if (vddio >= 3100 && vdda >= 3100) {
	
                /* Disable charge pump */	
		ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP;
		
		/* VDDC use VDDIO rail */
		lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
		lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
			    SGTL5000_VDDC_MAN_ASSN_SHIFT;
	} else {
		dev_info(codec->dev, "SGTL5000 will choose highest voltage automatically!\n");

                /* Disable charge pump */
		ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP;
		
		/* Switch to highest supply voltage */
		lreg_ctrl &= ~SGTL5000_VDDC_ASSN_OVRD;
	}

 

 We now have audio output on LINEOUT as expected.

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Contributor II

Hi,

I believe we have figured out what was going on. When we examined the power supply configuration code in the Linux driver, we saw the following (voltages here are given in mV):

 

if (vddio < 3100 && vdda < 3100) {
		/* enable internal oscillator used for charge pump */
		snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
					SGTL5000_INT_OSC_EN,
					SGTL5000_INT_OSC_EN);
		/* Enable VDDC charge pump */
		ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
	} else {
		ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP;
		/*
		 * if vddio == vdda the source of charge pump should be
		 * assigned manually to VDDIO
		 */
		if (regulator_is_equal(sgtl5000->supplies[VDDA].consumer,
				       sgtl5000->supplies[VDDIO].consumer)) {
			lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
			lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
				    SGTL5000_VDDC_MAN_ASSN_SHIFT;
		}
	}

 

As our intended VDDA supply was 3.3V, we did not require charge pump operation, so this branch was never invoked. The only other option supported, involving either VDDIO or VDDA exeeding 3.1V, then made a manual assignment of VDDC to the VDDIO supply. However, with our selection of VDDIO = 1.8V, this configuration would not allow the internal analogue switches in the SGTL5000 to operate. In other words, the stock Linux driver did not support VDDIO = 1.8V making it impossible for the device to produce audio output, despite appearing to operate correctly in every other sense.

On review of the SGTL5000 data sheet, it was apparent that an automatic voltage selection mode was actually supported, and the modified driver code snippet below was shown to reliably select VDDA as the source for VDDC in our configuration. This was confirmed by measuring 3.3V on pin 18 (CPFILT) of the chip.

 

if (vddio < 3100 && vdda < 3100) {

		/* enable internal oscillator used for charge pump */
		snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
					SGTL5000_INT_OSC_EN,
					SGTL5000_INT_OSC_EN);
		/* Enable VDDC charge pump */
		ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
	} else if (vddio >= 3100 && vdda >= 3100) {
	
                /* Disable charge pump */	
		ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP;
		
		/* VDDC use VDDIO rail */
		lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
		lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
			    SGTL5000_VDDC_MAN_ASSN_SHIFT;
	} else {
		dev_info(codec->dev, "SGTL5000 will choose highest voltage automatically!\n");

                /* Disable charge pump */
		ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP;
		
		/* Switch to highest supply voltage */
		lreg_ctrl &= ~SGTL5000_VDDC_ASSN_OVRD;
	}

 

 We now have audio output on LINEOUT as expected.

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NXP TechSupport
NXP TechSupport

Dear David,

 

I have checked the supply values and they are within the recommended boundaries. Please find attached AN3663 and SGTL5000 Silicon Errata. In the Errata document is a description of an issue with an internal regulator not starting.

 

With Best Regards,

Jozef

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Contributor II

Hi Jozef,

In relation to our earlier post about the lack of audio output from the SGTL5000 with Vddio = 1.8V, I should add that we have a Teensy breakout board running perfectly with Vddio = 3.3V using the same Linux driver code. Hence my question regarding special setup for 1.8V operation.

All clocks and data are being fed to the chip, with I2S data input to pin 25.

Can you confirm that customers are successfully using the SGTL5000 chip with Vddio = 1.8V?

Cheers,

David.

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Contributor II

Dear Jozef,

Thanks for confirming the voltages. While running the SGTL5000 with 

speaker-test -D hw:0,0 -c2 -r48000 -F S16_LE -t sine -f 1000

we see the following register values - Could you comment if you see anything that might prevent sound output from the Line Out (in view of the supply voltages)?

000: a011

002: 0061

004: 0008

006: 0130

00a: 0010

00e: 0200

010: 3c3c

014: 015f

020: 0000

022: 1818

024: 0022

026: 0020

028: 01f1

02a: 0000

02c: 0304

02e: 1f1f

030: 40f9

032: 5000

034: 0000

036: 0017

03a: 0000

03c: 0000

100: 0000

102: 0000

104: 0040

106: 051f

108: 0000

10a: 0040

10c: 0000

10e: 0000

110: 0000

116: 002f

118: 002f

11a: 002f

11c: 002f

11e: 002f

120: 8000

122: 0000

124: 0510

126: 1473

128: 0028

12a: 0050

12c: 0000

12e: 0000

130: 0000

132: 0000

134: 0000

136: 0000

138: 0000

13a: 0000

Best Regards,

David.

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NXP TechSupport
NXP TechSupport

Hi David,

please see a reply from an application engineer I have contacted. Please see the description and AN3664 attached. Please provide the required information.

 

DESCRIPTION

Please refer to the AN3664. Which is the SGTL5000 chip package used in customer design? Could customer provide schematic to review please?

If SGTL5000 chip package which customer used in their design is 32QFN, please let customer check the CPFILT pin(pin connection) connection method in customers design as in the snapshot attached.

 

With Best Regards,

Jozef

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