SGTL5000 route MIC input to headphone left and right output

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SGTL5000 route MIC input to headphone left and right output

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anthonynxp
Contributor II

Hi,

Does anyone know which registers need to be configured to route the MIC input to both the LEFT and RIGHT Headphone outputs?

Thanks in advance!

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anthonynxp
Contributor II

Since I can get audio from the LINEIN input to the HEADPHONE output, can you help me to route the LINEIN through the DAP? Because if  I can get that path to work, then I think it should be relatively easy to switch it to the MIC input. 

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reyes
NXP TechSupport
NXP TechSupport

Hi,

 

In that case the route would be: LINE_IN -> ADC -> DAP -> DAC -> HP_OUT

 

// Route LINE_IN to ADC

Modify CHIP_ANA_CTRL -> SELECT_ADC 0x0001 // bit 2

 

// Route ADC to DAP

Modify CHIP_SSS_CTRL -> DAP_SELECT 0x0000 // bits 7:6

 

// Route DAP to DAC

Modify CHIP_SSS_CTRL -> DAC_SELECT 0x0003 // bits 5:4

 

// Select DAC as the input to HP_OUT

Modify CHIP_ANA_CTRL -> SELECT_HP 0x0000 // bit 6

 

Regards,

Jose

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anthonynxp
Contributor II

Hi Jose,

Thank you for your help.

I've tried what you recommended, but I still cannot hear anything from the MIC input. I am successful in routing the LINEIN to the Headphone, but not the MIC input. Here is the code I am using. 

USHORT chipAnaHpCtrl = (
0x0 << 15 | // reserved
0x0 << 8 | // headphone right channel volume (0x00=+12.dB to 0x7f=-51.5dB 0.5dB steps)
0x0 << 0 // headphone left channel volume (0x00=+12.dB to 0x7f=-51.5dB 0.5dB steps)
);

USHORT chipAnaCtrl = (
0 << 9 | // reserved [15:9]
1 << 8 | // LINEOUT unmuted (should not matter)
0 << 7 | // reserved
0 << 6 | // Select the headphone input (0x0=DAC, 0x1=LINEIN) ************************
0 << 5 | // Disabled headphone zero cross detector (ZCD)
0 << 4 | // Unmute the headphone outputs
0 << 3 | // reserved
0 << 2 | // Select ADC input (0x0=Microphone, 0x1=LINEIN) ***************************
0 << 1 | // Disable ADC analog zero cross detector (ZCD)
1 << 0 // Mute the ADC analog volume
);

USHORT chipSssCtrl = (
0 << 15 | // reserved
0 << 14 | // DAP mixer input swap (0=normal operation, 1=left and right channels of DAP mixer are swapped)
0 << 13 | // DAP input swap (0=normal operation, 1=left and right channels of DAP mixer are swapped)
0 << 12 | // DAC input swap (0=normal operation, 1=left and right channels of DAP mixer are swapped)
0 << 11 | // reserved
0 << 10 | // I2S DOUT swap (0x0=normal operation, 0x1=left & right channels of I2S are swapped)
0 << 8 | // [9:8] Select data source for DAP mixer (0=ADC, 1=I2S_IN, others reserved)
0 << 6 | // [7:6] Select data source for DAP (0=ADC, 1=I2S_IN, others reserved)
0 << 4 | // [5:4] Select data source for DAC (0=ADC, 1=I2S_IN, 2=reserved, 3=DAP) ************************
0 << 2 | // [3:2] reserved
0 << 0 // [1:0] Select data source for I2S_DOUT (0=ADC, 1=I2S_IN, 2=reserved, 3=DAP)
);

USHORT dapCtrl = (
0 << 5 | // reserved [15:5]
0 << 4 | // Enable/Disable DAP mixer path (0x0=Disabled)
0 << 1 | // reserved [3:1]
1 << 0 // Enable/Disable DAP (0x0=Disable, no audio passes through, 0x1=Enable, when enabled, audio can pass through DAP even if none of the DAP functions are enabled)
);

USHORT dapPeq = (
0 << 3 | // reserved [15:3]
0 << 0 // Set to Enable the PEQ filters (0x0=Disabled)
);

USHORT dapBassEnhance = (
0 << 9 | // reserved [15:9]
1 << 8 | // bypass high pass filter
0 << 7 | // reserved
4 << 4 | // set cut-off frequency (0x4=175Hz)
0 << 1 | // reserved [3:1]
0 << 0 // disable Bass Enhance
);

USHORT dapAudioEq = (
0 << 2 | // reserved [15:2]
0 << 0 // [1:0] PEQ/GEQ/Tone control and enable/disable it (0=disabled)
);

USHORT dapSgtlSurround = (
0 << 7 | // reserved [15:7]
4 << 4 | // freescale surround width control (0x0=Least width)
0 << 2 | // reserved [3:2]
0 << 0 // disble Freescale Surround Selection
);

USHORT chipDigPower = (
0 << 7 | // reserved
1 << 6 | // enable ADC block, both digital and analog
1 << 5 | // enable DAC block, both analog and digital
1 << 4 | // enable DAP block
0 << 2 | // [3:2] reserved
0 << 1 | // disable i2s data output
0 << 0 // disable i2s data input
);

USHORT chipAnaAdcCtrl = (
0x0 << 9 | // [15:9] reserved
0x0 << 8 | // ADC volume range reduction (oxo=no change in ADC range, 0x1=ADC range reduced by 6.0dB
0xF << 4 | // [7:4] ADC right channel volume (0x0=0dB .. 0xF=+22.5dB)
0xF << 0 // [3:0] ADC left channel volume (0x0=0dB .. 0xF=+22.5dB)
);

USHORT chipMicCtrl = (
0x0 << 10 | // [15:10] reserved
0x0 << 8 | // [9:8] MIC bias output impedance adjustment
0x0 << 7 | // reserved
0x0 << 4 | // [6:4] MIC bias voltage adjustment 0x0=1.25V
0x0 << 2 | // [3:2] reserved
0x1 << 0 // [1:0] MIC amplifier gain (0x0=0dB, 0x1=+20dB, 0x2=+30dB, 0x3=+40dB)
);

USHORT chipAdcDacCtrl = (
0x0 << 14 | // [15:14] reserved
0x0 << 13 | // ReadOnly - Volume busy dac right
0x0 << 12 | // ReadOnly - Volume busy dac left
0x0 << 10 | // [11:10] reserved
0x0 << 9 | // Volume ramp enable - disabled
0x0 << 8 | // Exponential volume ramp enable - disabled
0x0 << 4 | // [7:4] reserved
0x0 << 3 | // DAC right mute - unmuted
0x0 << 2 | // DAC left mute - unmuted
0x0 << 1 | // ADC high pass filter freeze - normal operation
0x1 << 0 // ADC high pass filter bypass - bypassed and offset not updated
);

i2cWrite(i2c, 0x0022 /* SGTL5000_CHIP_ANA_HP_CTRL */, chipAnaHpCtrl );
i2cWrite(i2c, 0x0024 /* SGTL5000_CHIP_ANA_CTRL */, chipAnaCtrl );
i2cWrite(i2c, 0x000A /* SGTL5000_CHIP_SSS_CTRL */, chipSssCtrl );
i2cWrite(i2c, 0x0100 /* SGTL5000_DAP_CONTROL */, dapCtrl );
i2cWrite(i2c, 0x0102 /* SGTL5000_DAP_PEQ */, dapPeq );
i2cWrite(i2c, 0x0104 /* SGTL5000_DAP_BASS_ENHANCE */, dapBassEnhance );
i2cWrite(i2c, 0x0108 /* SGTL5000_DAP_AUDIO_EQ */, dapAudioEq );
i2cWrite(i2c, 0x010A /* SGTL5000_DAP_SGTL_SURROUND */, dapSgtlSurround );
i2cWrite(i2c, 0x0002 /* SGTL5000_CHIP_DIG_POWER */, chipDigPower );
i2cWrite(i2c, 0x0020 /* SGTL5000_CHIP_ANA_ADC_CTRL */, chipAnaAdcCtrl );
i2cWrite(i2c, 0x002A /* SGTL5000_CHIP_MIC_CTRL */, chipMicCtrl );
i2cWrite(i2c, 0x000E /* SGTL5000_CHIP_ADCDAC_CTRL */, chipAdcDacCtrl );

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reyes
NXP TechSupport
NXP TechSupport

Hi,

 

The route should be as follows:

MIC -> ADC -> DAC -> HP_OUT

 

Here is what you need to configure to set this route:

 

// MIC -> ADC

// Select MIC as the input to ADC

CHIP_ANA_CTRL -> SELECT_ADC = 0x0  // bit 2

 

// ADC -> DAC

// Select ADC as the input to DAC

CHIP_SSS_CTRL -> DAC_SELECT = 0x0 // bits 5:4

 

// DAC –> HP

// Select DAC as the input to HP_OUT

CHIP_ANA_CTRL -> SELECT_HP = 0x0  // bit 6

 

And you can use CHIP_ANA_HP_CTRL register to control the volume on both Headphone Right and Headphone Left channels

 

Regards,

Jose

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