SGTL5000 audio codec sample rate

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SGTL5000 audio codec sample rate

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DustyStew
Contributor V

I don't understand how the SGTL5000 sets it's sample clock. There are 2 bits in a register that specify 32k/44k1/48k/96k sampling. This clearly is a map to a prescaler for a clock generator. The problem is: how does one set the sample rate to (say) 22050 or 8000?

One solution would be to select a sample rate that is a multiple of the desired, then duplicate or interpolate samples to match the sample rate setting on the SGTL5000 (when playing). For recording, the samples could be averaged to reduce the sample rate.

However this requires work on the MCU. You can't just read a block from a file and DMA it to the I2S port.

Is there are solution to this? I am using a K20 MCU.

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DustyStew
Contributor V

I sorted this out. I didn't notice there were two more bits that modified the sample rate setting to be x1. x1/2 x1/4 and x1/6. All fine and well. I presume the idea is that the source clock must (generally) be 256xFs, and so you've got to generate a source clock that is 256x whichever of the 4 sample rate (32k,44k1, 48k, 96k) that you choose. Then if you want to use a sub-multiple, change those other 2 bits accordingly.

BTW it looks as if the PLL inside the SGTL can only be programmed once out of reset. So that is not a solution for a system that needs to play various audio files. And Processor Expert does not know how to configure the I2S peripheral (which they call SSI) to generate the desired MCLK frequencies. There is a fractional divider, with two fields, FRACT and DIVIDE. There are something like 1 million combinations of these two values.  My solution was to write a script that calculated the ratio for all combinations and printed out the one that was closest to the desired frequency.

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143 Views
DustyStew
Contributor V

I sorted this out. I didn't notice there were two more bits that modified the sample rate setting to be x1. x1/2 x1/4 and x1/6. All fine and well. I presume the idea is that the source clock must (generally) be 256xFs, and so you've got to generate a source clock that is 256x whichever of the 4 sample rate (32k,44k1, 48k, 96k) that you choose. Then if you want to use a sub-multiple, change those other 2 bits accordingly.

BTW it looks as if the PLL inside the SGTL can only be programmed once out of reset. So that is not a solution for a system that needs to play various audio files. And Processor Expert does not know how to configure the I2S peripheral (which they call SSI) to generate the desired MCLK frequencies. There is a fractional divider, with two fields, FRACT and DIVIDE. There are something like 1 million combinations of these two values.  My solution was to write a script that calculated the ratio for all combinations and printed out the one that was closest to the desired frequency.

View solution in original post

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