I am seting up the SC16IS750 on a Linux development (Wayland on IMX8MM) and I need to be able to retrieve single bytes from the SC16IS7xx from the communications bus. One of the issues I have is that the standard Linux drivers take so long in requesting the data byte received it has been overwritten before any byte are actually collected on the I2C bus.
So this setup is FIFO off giving me an IRQ at the end of the first byte. However I don't get a start signal from the Linux SDA line until 900uS after the IRQ, which is why I am losing the data and is obviously a Linux issue). I had the unit working with the FIFO and triggering on four bytes (minimum with the FIFO on), however this isn't any good for the system I am working on as there are a lot of single byte Acknowledges from the connected devices.
White trace is SCL, Orange is SDA and red is the RX recieve.
So my question is can I have a FIFO and a trigger level of 1 byte?
Thanks in advance.
Glenn Aitchison
Tried to just replacee with the current file and the build is complaining about the mach/*.h files.
Hi Jozef, thanks for that, I will read through the drivers files to get a better understanding, I am using Yocto to build the Linux kernel, do I just need to replace the SC16IS7xx.c file with the one attached and include the header file in the same directory?
Glenn
Hello Glen,
I would like to contact an application engineer with the issue. But the application engineers require information below. Could you please provide?
Customer: Altilium-engineering
End Customer: ?
End Application: ?
Country: United Kingdom
Annual Volume: ?
With Best Regards,
Jozef
Ho Josef, no problem.
I am contracting for a company called VMS Newco they manufacture Variable Message signs for the Highways Agency as well as Internation transport groups.
So the final customer for this is VMS Nemwco/ Highways Agency.
End application is a Variable message sign controller, this contains an imx8mm SOC, Symphony board and 3 off SC16IS750 uarts each. Overall quantity for the highways agency is around 250 imx8mm per annum and 750 SC16IS550. I don't have anythings for the other international clients.
Best regards
Glenn Aitchison
Hello Glen,
please see below an answer from an application engineer I have contacted.
DESCRIPTION
The minimum receive interrupt trigger level is 4 bytes. This device does not support one byte receive interrupt trigger level.
With Best Regards,
Jozef
Hi Jozef, that isn't quite correct.
The SC16IS7XX will give a single byte interrupt if the FIFO is off. See image attached.
Is the FE saying there is no way to have FIFO on and a single byte interrupt?
Can you try the IMX8MM team and see how I implement the SC16IS7XX driver that you sent in Yocto, I would like to try this as it seems to creat a software buffer and looks like it could be my solution. If I get the I2C timing issues sorted out.
Glenn
Hi Glen,
I have created a new ticket and moved it in iMX box. There is also a reference to this thread. An support representative from the iMX team will answer you here.
With Best Regards,
Jozef
Thanks Josef, one quick question, does the SC16IS750 employ clock stretching, one of the forum questions noticed that the clock line is held low during the delay.
Best regards
Glenn
Hi Glen,
Unfortunately no, SC16IS750 does not support clock stretching.
With Best Regards,
Jozef