Update: Nevermind, I fixed it, my baud rate generator clock was pausing because I had a breakpoint set right after the test function. PEBKAC.
The screenshot I have attached shows what I'm seeing in my logic analyzer. Signal lines from top-to-bottom are:
TX interpreter
TX line level
Chip-select to the SC16IS750
Interpreter for MOSI
MOSI line level
CLK to SC16IS750
Another copy of CS
Interpreter for MISO
MISO line level
Another copy of CLK
The "C0" command first verifies that there is room in the FIFO to print my test string "54321". After toggling CS, The "00" command begins a FIFO write, and the logic analyzer shows all characters being sent correctly over SPI, and the logic probe connected to the UART TX line also shows that the first four characters are transmitted successfully. However, as soon as the CS line is deasserted on SPI after sending the fifth character, a framing error occurs on the UART. You can see the SC161S750 is actually holding the TX line low for some reason. I'm going to try different clocks, delays, etc. but I thought I would post here first in case there's some known errata or weirdness I should be aware of. I didn't see an errata sheet on the product page for SC16IS750.
The SPI clock is 1 MHz, the baud rate generator clock is 16.3333... Mhz, the baud divider register is set to "1" on the SC16IS750, which yields a baud rate of 1.02Mbaud.
It works fine if I do things the very slow way, alternating between reads of the LSR to see if I can transmit, then writing a character to the TX register if the LSR says I can, but that of course slows down the throughput considerably, so I'd much rather use the FIFO functionality if I can make it work correctly.
