S32R45:Does PCIe1 work as Root Complex mode on the S32R45 EVB board?

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S32R45:Does PCIe1 work as Root Complex mode on the S32R45 EVB board?

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MeiMei
Contributor I

      Hardware:S32R45 EVB

      The nvme ssd with the M.2 port is inserted into the Pcie to M.2 adapter card, and the pcie to pcie extension cable is connected to the EVB board Pcie1 and the adapter card.

      Connect as shown below:

MeiMei_1-1679631136986.png

      Q: Is this mode supported?

      In u-boot mode, set hwconfig to RC mode. The following figure shows the command:
      Reset and restart, the ssd device cannot be identified.

MeiMei_0-1679630423300.png

 

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petervlna
NXP TechSupport
NXP TechSupport

Hello,

The processor board has a PCIe end point connector on SERDES1 lane 0.
Both lanes of the S32R45 SERDES0 interface are routed to the PCIe root complex connector on the platform board.

petervlna_0-1680078215259.png

S32R45 PCIe can be configured as EP or RC mode.

For S32R45 EVB if you wants to use PCIe1 as RC mode, you have to deal with clocking.

So please use PCIe0 if you want to use RC mode and need not change anything .

Best regard,

Peter

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MeiMei
Contributor I

For S32R45 EVB board, I want to use PCIE1 lane0 as RC mode, what processing needs to be done to the clock?

1. We set PCIE1 to RC mode and clock to int. The error is shown as follows:

    PCIe1:Failed to get link up       

    Execute pci instruction:No PCIe device was found in bus 0

MeiMei_0-1680080527859.png

2. We set PCIE1 to RC mode and set the clock to ext. The error is shown as follows:

     Failed to lock PCIe phy     (I don't know whether it is the fault of PCIe1)

     Failed to power on 'serdes_lane0' PHY     (I don't know whether it is the fault of PCIe1)

     Execute pci instruction:No PCIe device was found in bus 0

MeiMei_1-1680080624188.png

 

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petervlna
NXP TechSupport
NXP TechSupport

Hello,

For R45EVB SERDES1, it has a EP connector, which will get the clock form external device, such as RC. So if you wants to use SERDES1 as RC, you should provide separate 100M clock. It requires the other hardware solutions to make sure both RC and EP get a 100MHz clock.

petervlna_0-1680252971654.png

Best regards,

Peter

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petervlna
NXP TechSupport
NXP TechSupport

Hello,

I have asked RADAR team to have a look at your query.

Best regards,

Peter

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