PTN3460 : in the datasheet pin 14 and 15 are noted "Not connected" in the application note UM10492 these two pins are connected together. Is there an explanation ?

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PTN3460 : in the datasheet pin 14 and 15 are noted "Not connected" in the application note UM10492 these two pins are connected together. Is there an explanation ?

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Contributor I

In the datasheet pin 15 and 16 are noted "Not connected", in the application note UM10492 page 11 fig 6, pin 15 and 16 are connected together, is there a reason for that ?

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NXP TechSupport
NXP TechSupport

Hello Bernard,

PTN3460/3460I evaluation board was designed for multiple test.
 
Though pin 15, 16 are shown to connect to SW_OUT, SW_OUT portion of circuitry is not loaded.
image004 (2).png
We simplify the application design shown on datasheet.
 
Please leave pin 15, 16 NC on your design, either PTN3460 or PTN3460I.
Best regards,
Tomas
 
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Contributor I

Hi Tomas,

the customer come back to me with some questions :

- in front of PTN3460 there is an Exynos Samsung (nobody's perfect :smileyshocked:), for this reason there are some capacitor 100 nF on DP_LANE.

But there is no capacitor on pins AUX_P and AUX_N (PTN3460 side).

Question is : is it possible to avoid these two capacitor

Is it possibkle to move pul-up and pull-down resistors on AUX pin or is it necessary to add the missing capacitor ?

This is the schematics

PTN3460-InSituation.jpg

Thank you for help.

Bernard

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NXP TechSupport
NXP TechSupport

Hello Bernard,

First off, please accept my apologies for the delay in answering this question, I probably overlooked it.

Only one set of caps are necessary for DP_Lanes and AUX.
Hence, if there are already 100nF on DP_LANE P/N traces, then C80-C83 can be removed.
If there are no capacitors on AUX_P and AUX_N on Exynos Samsung side, then C84-C85 are necessary.
Pull-up and pull-down on AUX pins are not necessary for on board design. They can be no-load.
Best regards,
Tomas
 
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