PTN3460 Master Mode EDID location

キャンセル
次の結果を表示 
表示  限定  | 次の代わりに検索 
もしかして: 

PTN3460 Master Mode EDID location

ソリューションへジャンプ
2,233件の閲覧回数
jasonee
Contributor I

Hello --

We are using a PTN3460 to translate DisplayPort data to LVDS. We are finding that the EDID data that is stored in the EEPROM is not being sent to the PC the display is hooked up to. It seems that the configuration data is being read, as we can display an image on the display in question, but it takes a considerable amount of configuration on the PC side to get this to work. Essentially, we are inputting the EDID data manually on the PC side to get the timing on the display to work.

One thing that's not clear, which we believe is the core issue, is that we do not understand where in SRAM the external EDID data is transferred. The default for EDID emulation control (configuration register 0x84) is 0x09, which point to EDID 4. The RAM map shows that the configuration data for the part gets stored at the end of RAM, which suggests that the EDID data is stored in EDID 6, since this would be a continuous read of the external EEPROM. I could also understand this being put in EDID 0, since it is the first one, and at the top of the RAM mapping.

The programming guide is not clear. Other than this issue, everything seems to work. Any help would be appreciated.

Thanks

#ptn3460‌, #display

タグ(2)
1 解決策
1,731件の閲覧回数
TomasVaverka
NXP TechSupport
NXP TechSupport

Hello Jason,

The external EEPROM only stores one EDID (0x00 – 0x7F) and configuration registers (0x80 – 0xFF).

 

If external EEPROM is used (DEV_CFG pin = high) in application, then firmware will read EDID from external EEPROM data address 0x00-0x7F to overwrite the EDID 0 in SRAM , and read configuration registers from external EEPROM data address 0x80-0xFF to overwrite configuration registers in SRAM during power up (firmware initialization) phase.

 

You need to set configuration 0x84 (EPROM data address 0x84) = 0x01, so that the EDID 0  (external EEPROM 0x00 – 0x7F) will be used to send to the DP source (PC).

 

So in short, if you want to use external EEPROM in application, than you need to set configuration register 0x84 = 0x01 and write EDID in the EEPROM data address 0x00-0x7F, so the EDID will be sent to the DP source (PC).

Best regards,

Tomas

元の投稿で解決策を見る

2 返答(返信)
1,732件の閲覧回数
TomasVaverka
NXP TechSupport
NXP TechSupport

Hello Jason,

The external EEPROM only stores one EDID (0x00 – 0x7F) and configuration registers (0x80 – 0xFF).

 

If external EEPROM is used (DEV_CFG pin = high) in application, then firmware will read EDID from external EEPROM data address 0x00-0x7F to overwrite the EDID 0 in SRAM , and read configuration registers from external EEPROM data address 0x80-0xFF to overwrite configuration registers in SRAM during power up (firmware initialization) phase.

 

You need to set configuration 0x84 (EPROM data address 0x84) = 0x01, so that the EDID 0  (external EEPROM 0x00 – 0x7F) will be used to send to the DP source (PC).

 

So in short, if you want to use external EEPROM in application, than you need to set configuration register 0x84 = 0x01 and write EDID in the EEPROM data address 0x00-0x7F, so the EDID will be sent to the DP source (PC).

Best regards,

Tomas

1,731件の閲覧回数
jasonee
Contributor I

Thank you Tomas. Selecting EDID 0 made everything work correctly with the external ROM.

0 件の賞賛
返信