I am developping a bootloader for the T1042 processor, on the T1042D4RDB board.
I successfully configured the RCW for booting from SPI NOR Flash. BPI instructions configure the ALTCBAR for access to the CPC as 256 kB SRAM, and correctly loads the code inside it.
This code is executed, and I can create some new TLBs and LAWs to try to access more memory (than the 4 kb Boot sector, and 256 kB SRAM) on the system. These TLBs and LAWs seem correctly created, since I can look at them via Trace32 Lauterbach debug tool.
And now the problem :
When the code access any address, nothing happen; I see the code trying to write, for example with the stw assembly instruction, but the target address is not modified, even the SRAM is not written to.
Any suggestion is welcome.
Here are some registers :
Local Access Window 11 (this is formerly what I want to access to configure the DDR)
LAWBARH11 00000000 BASE_ADDR_HIGH 0x0 ^DUMP+
LAWBARL11 FE008000 BASE_ADDR_LOW FE008000
LAWAR11 81C0000F EN Enabled TRGT_ID 1C SIZE 64 KBytes
Local Access Window 12 (this the LAW to the SRAM)
LAWBARH12 00000000 BASE_ADDR_HIGH 0x0 ^DUMP+
LAWBARL12 FFFC0000 BASE_ADDR_LOW FFFC0000
LAWAR12 81000011 EN Enabled TRGT_ID 10 SIZE 256 KBytes
Local Access Window 13 (this is a LAW to the -hopefully configured- DDR)
LAWBARH13 00000000 BASE_ADDR_HIGH 0x0 ^DUMP+
LAWBARL13 80000000 BASE_ADDR_LOW 80000000
LAWAR13 81C0001E EN Enabled TRGT_ID 1C SIZE 2 GBytes
Configuration, control, and status registers
CCSRBARH 00000000 BASE_ADDR_HIGH 0x0
CCSRAR 00000000 C No effect
Alternate configuration registers
ALTCBARH 00000000 BASE_ADDR_HIGH 0x0
ALTCAR 00000000 EN Disabled TRGT_ID 00
Boot Space Translation Registers
BSTRH 00000000 TRANS_ADDR_HIGH 0x0
BSTAR 01F0000B EN Disabled TRGT_ID 1F SIZE 4 KB
A:FFFFF000--FFFFFFFF : pages size 4kB IPROT -I-G- U--- SRWX
A:FE000000--FE3FFFFF : pages size 4MB IPROT ----- URWX SRWX
A:FFFC0000--FFFFFFFF : pages size 256kB IPROT ----- URWX SRWX
A:00000000--FFFFFFFF : pages size 4GB IPROT ----- URWX SRWX
Thanks for your help
> LAWAR11 81C0000F EN Enabled TRGT_ID 1C SIZE 64 KBytes
> LAWAR13 81C0001E EN Enabled TRGT_ID 1C SIZE 2 GBytes
Why "1C" is used?
Why LAW13 is overlapping CCSR? For recommended memory map please refer to the QorIQ T1040 Reference Manual, 2.3.5 Local Address Map Example.