PCIe occur polling.compliance error on S32R45

[aiweixin]

Hi,

    On our S32R45 board, the REFCLK of PCIe_1 have connect to external 100MHz clock, and setenv hwconfig "pcie0:mode=ep,clock=int;pcie1:mode=rc,clock=ext" in uboot.

    Reboot the system, PCIe_1 occur polling.compliance error.

    atf version: release/bsp33.0-2.5

    uboot version: release/bsp33.0-2020.04

    linux version: release/bsp33.0-5.10.109-rt

    Why? and how to make it ok?

[petervlna]

Hello,

Please submit a ticket at nxp.com so I can escalate this question to RADAR team.

https://community.nxp.com/t5/HomeTest-Knowledge-Base/How-to-submit-a-new-question-for-NXP-Support/ta...

Best regards,

Peter