PCF2129T reset time register after power up

[fernandoalcaide]

Dear,

I am using your RTC, reference PCF2129T, in one board designed by us. I am connected VDD to 3V3 and VBAT to external battery.

After one power down of VDD and power up, I am reading the time registers and the value has been reset.

I am monitoring VBAT all time and the value is adove of 3V

Do you know what is the problem?

Could you say me one idea?

Thank you in advance

[tech4]

Hello Fernando,

Do you still confirm such problem and possibly elaborate what you saw because we also noticed very strange problems with PCF2129T on boards we are using for years with the exact same Linux system version.

In the begining of 2020, we noticed that date behavior was very eratic.

After many tests, we noticed that the problem came from PCF2129T with date code D19252 because other date codes such as D18432, D16482, D17522 were working fine even of boards supposed to be not working.

So we asked our board supplier to buy date code before D19252 to be confident. They found some D16452 and in fact these ones don't work either, they are going back the time!

Did you notice similar things?

Best regards,

Alain

[reyes]

Hi ,

The PCF2129 has a backup battery input pin and backup battery switch-over circuit which monitors the main power supply. The backup battery switch-over circuit automatically switches to the backup battery when a power failure condition is detected.

The power management functions are controlled by the control bits PWRMNG[2:0] (see Table 19) in register Control_3 (see Table 11).

I’m assuming that for your system, you have the default setting for these bits, which are ‘00’ and means that battery switch-over function is enabled in standard mode; and battery low detection function is enabled.

When battery switch-over function is set in standard mode, the power failure condition happens when VDD < VBAT AND VDD < Vth(sw)bat

Vth(sw)bat is the battery switch threshold voltage which is 2.5 V, so this should not be the problem since your battery is always above 3.0V.

So, other possibility would be the power down slew rate.

Several users have application-related concerns when they power-down VDD. VDD ramp down too fast seems to be the most possible cause of the behavior you are seen.

VDD is sampled. If it collapses in between samples then the event is missed and the device fails to switch to battery.

Please ensure that you keep the slew rate at 0.7V/ms or less. If the slew rate is faster than 0.7V/ms, then you can slow it down by adding some decoupling capacitors on the VDD pin.
The functionality of the battery switch-over is limited by the fact that the power supply VDD is monitored every 1 ms in order to save power consumption. Considering that the battery switch-over threshold value (Vth(sw)bat) is typically 2.5 V, the power management operating limit (VDD(min)) is 1.8 V and that VDD is monitored every 1 ms, the battery switch-over works properly in all cases where VDD falls with a rate lower than 0.7 V/ms.

I recommend you to check the Application Note AN1186 where you can find more details information about this topic, especially on section 5.3 “Battery switch-over applications”: https://www.nxp.com/docs/en/application-note/AN11186.pdf

Regards,

Jose

NXP Semiconductors