Dear G.W,
Thanks for the reply, I could share the Altium schematics, please let me know if it would be useful.
I can describe the conditions of the test:
The Duty Cycle in the 1kHz PWM was set to 50%, attached you can find pictures of the described behavior. Sorry for the quality, but because of quarantine I can't access any other scope. The 3 pictures attached were measured with a 166Hz square wave, 50% duty cycle. There seems to be a delay between the OE rising edge (OE is negated) and the falling edge of the selected output pin. Changing the polarity of OE by software, by using the OEPOL bit in the MODE SELECTION REGISTER seems to have no effect, the delay is still present on the falling edge of the selected output pin. The delay is aprox 1-1.5ms long (pictures are taken with some persistence so they are not 100% accurate). Changing duty cycle does not affect the delay, just the relative position of it. Because the delay is larger than 1ms the maximum switching frequency is limited by it, faster than that it doesn't switch off. There seems to be a 80us jitter (peak to peak) on the falling edge of the output pin (delay). The supplied voltage is 5VUSB, 4.9V in the Vdd pins of the PCA9698, 4.7-4.8V measured at the output pin when the OE is selected . 2x100nF capacitors, one in each Vdd pin, together with a 33uF capacitor are used to decouple each IC. Seven PCA9698 are used in a 150x300 board, the output conditions for all the pins (250 pins) is a 10kOhm load.
