PCA9616 specification questions at Differencial I2C bus operation.

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PCA9616 specification questions at Differencial I2C bus operation.

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Yoshidaj
Contributor I

PCA9616 Datasheet P.11 show as below.

Due to the SMBus/I2C-bus handshake protocol (ACK/NACK on the ninth clock pulse), the direction of the SMBus/I2C-bus is reversed often.

 

< Question >

1) What's the condition that I2C bus direction of the SMBus/I2C-bus reversed.

2) When reveresed the direction, what's the timming and time for the revered.

 

We couldn't confime on the Datasheet, please let us know it.

 

 

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JozefKozon
NXP TechSupport
NXP TechSupport

Dear Yoshidaj,

 

1) What's the condition that I2C bus direction of the SMBus/I2C-bus reversed.

[A] The bus path is bidirectional. Assume that the left side SMBus/I2C-bus becomes active. A
START condition (SDA goes LOW while SDA is HIGH) is sent. This upsets the idle
condition on the dI2C-bus section of the bus, because D+ was more positive than D- and now they are reversed. The right side bus buffer sees the differential lines change polarity
and in turn pulls SDA LOW on the SMBus/I2C-bus side of the bus buffer, transmitting the
START condition to the slave on that section of the SMBus/I2C-bus.

If the data clocked out by the left side master contains a valid address of the right side
slave, that slave responds by pulling SDA LOW on the ninth clock. This condition is
transmitted across the dI2C-bus section that has now changed flow direction, and
received by the left side bus buffer (again, D+ was more positive than D- and now they
are reversed).

This sequence continues until the master sends the STOP condition (SCL HIGH while
SDA goes HIGH), placing the active slave (on the right side) back to idle. When idle, the
normal SMBus/I2C-bus (both left and right sections) are pulled up by their respective
pull-ups. In turn, the dI2C-bus section of the bus rests with D+ more positive than D-.

2) When reversed the direction, what's the timing and time for the revered.

[A] This depend on the SMBus/I2C-bus protocol. Up to 100 kHz (Standard
mode), 400 kHz (Fast mode), or up to 1 MHz (Fast-mode Plus).

 

With Best Regards,

Jozef

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JozefKozon
NXP TechSupport
NXP TechSupport

Dear Yoshidaj,

 

1) What's the condition that I2C bus direction of the SMBus/I2C-bus reversed.

[A] The bus path is bidirectional. Assume that the left side SMBus/I2C-bus becomes active. A
START condition (SDA goes LOW while SDA is HIGH) is sent. This upsets the idle
condition on the dI2C-bus section of the bus, because D+ was more positive than D- and now they are reversed. The right side bus buffer sees the differential lines change polarity
and in turn pulls SDA LOW on the SMBus/I2C-bus side of the bus buffer, transmitting the
START condition to the slave on that section of the SMBus/I2C-bus.

If the data clocked out by the left side master contains a valid address of the right side
slave, that slave responds by pulling SDA LOW on the ninth clock. This condition is
transmitted across the dI2C-bus section that has now changed flow direction, and
received by the left side bus buffer (again, D+ was more positive than D- and now they
are reversed).

This sequence continues until the master sends the STOP condition (SCL HIGH while
SDA goes HIGH), placing the active slave (on the right side) back to idle. When idle, the
normal SMBus/I2C-bus (both left and right sections) are pulled up by their respective
pull-ups. In turn, the dI2C-bus section of the bus rests with D+ more positive than D-.

2) When reversed the direction, what's the timing and time for the revered.

[A] This depend on the SMBus/I2C-bus protocol. Up to 100 kHz (Standard
mode), 400 kHz (Fast mode), or up to 1 MHz (Fast-mode Plus).

 

With Best Regards,

Jozef

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